Commit 3aba0b40 authored by Xin Li (Intel)'s avatar Xin Li (Intel) Committed by Borislav Petkov (AMD)
Browse files

x86/cpufeatures: Shorten X86_FEATURE_AMD_HETEROGENEOUS_CORES 



Shorten X86_FEATURE_AMD_HETEROGENEOUS_CORES to X86_FEATURE_AMD_HTR_CORES
to make the last column aligned consistently in the whole file.

No functional changes.

Suggested-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: default avatarXin Li (Intel) <xin@zytor.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/20250415175410.2944032-4-xin@zytor.com
parent 13327fad

arch/x86/include/asm/cpufeatures.h

+1 −1
Original line number Diff line number Diff line
@@ -478,7 +478,7 @@ 
#define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* BHI_DIS_S HW control enabled */

#define X86_FEATURE_CLEAR_BHB_VMEXIT	(21*32+ 4) /* Clear branch history at vmexit using SW loop */

#define X86_FEATURE_AMD_FAST_CPPC	(21*32+ 5) /* Fast CPPC */

#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32+ 6) /* Heterogeneous Core Topology */

#define X86_FEATURE_AMD_HTR_CORES	(21*32+ 6) /* Heterogeneous Core Topology */

#define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32+ 7) /* Workload Classification */

#define X86_FEATURE_PREFER_YMM		(21*32+ 8) /* Avoid ZMM registers due to downclocking */

arch/x86/kernel/acpi/cppc.c

+1 −1
Original line number Diff line number Diff line
@@ -272,7 +272,7 @@ int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator) 
	}



	/* detect if running on heterogeneous design */

	if (cpu_feature_enabled(X86_FEATURE_AMD_HETEROGENEOUS_CORES)) {

	if (cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES)) {

		switch (core_type) {

		case TOPO_CPU_TYPE_UNKNOWN:

			pr_warn("Undefined core type found for cpu %d\n", cpu);

arch/x86/kernel/cpu/scattered.c

+1 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ static const struct cpuid_bit cpuid_bits[] = { 
	{ X86_FEATURE_PERFMON_V2,		CPUID_EAX,  0, 0x80000022, 0 },

	{ X86_FEATURE_AMD_LBR_V2,		CPUID_EAX,  1, 0x80000022, 0 },

	{ X86_FEATURE_AMD_LBR_PMC_FREEZE,	CPUID_EAX,  2, 0x80000022, 0 },

	{ X86_FEATURE_AMD_HETEROGENEOUS_CORES,	CPUID_EAX, 30, 0x80000026, 0 },

	{ X86_FEATURE_AMD_HTR_CORES,		CPUID_EAX, 30, 0x80000026, 0 },

	{ 0, 0, 0, 0, 0 }

};

arch/x86/kernel/cpu/topology_amd.c

+1 −1
Original line number Diff line number Diff line
@@ -182,7 +182,7 @@ static void parse_topology_amd(struct topo_scan *tscan) 
	if (cpu_feature_enabled(X86_FEATURE_TOPOEXT))

		has_topoext = cpu_parse_topology_ext(tscan);



	if (cpu_feature_enabled(X86_FEATURE_AMD_HETEROGENEOUS_CORES))

	if (cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES))

		tscan->c->topo.cpu_type = cpuid_ebx(0x80000026);



	if (!has_topoext && !parse_8000_0008(tscan))

tools/arch/x86/include/asm/cpufeatures.h

+1 −1
Original line number Diff line number Diff line
@@ -468,7 +468,7 @@ 
#define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* BHI_DIS_S HW control enabled */

#define X86_FEATURE_CLEAR_BHB_VMEXIT	(21*32+ 4) /* Clear branch history at vmexit using SW loop */

#define X86_FEATURE_AMD_FAST_CPPC	(21*32+ 5) /* Fast CPPC */

#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32+ 6) /* Heterogeneous Core Topology */

#define X86_FEATURE_AMD_HTR_CORES	(21*32+ 6) /* Heterogeneous Core Topology */

#define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32+ 7) /* Workload Classification */

#define X86_FEATURE_PREFER_YMM		(21*32+ 8) /* Avoid ZMM registers due to downclocking */