Commit 3b3c9e86 authored by Sunil Khatri's avatar Sunil Khatri Committed by Alex Deucher
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drm/amdgpu: add se registers to ip dump for gfx10 



add the registers of SE block of gfx for ip dump
for gfx10 IP.

Signed-off-by: default avatarSunil Khatri <sunil.khatri@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b4e394e8

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+6 −1
Original line number Diff line number Diff line
@@ -373,7 +373,12 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = { 
	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP)

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP),

	/* SE status registers */

	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),

	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),

	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),

	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)

};



static const struct soc15_reg_golden golden_settings_gc_10_1[] = {