Commit 3c5aa4c7 authored Nov 17, 2022 by Bryan O'Donoghue Committed by Bjorn Andersson Dec 06, 2022

arm64: dts: qcom: sm8250: camss: Define ports and ports address/size cells

Define the set of possible ports, one for each CSI PHY along with the port
address and size cells @ the SoC dtsi level.

Suggested-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221117003232.589734-7-bryan.odonoghue@linaro.org

parent 64cb4a44

arch/arm64/boot/dts/qcom/sm8250.dtsi

+29 −0

Original line number	Diff line number	Diff line
		@@ -3908,6 +3908,35 @@ camss: camss@ac6a000 {
		"cam_hf_0_mnoc",
		"cam_sf_0_mnoc",
		"cam_sf_icp_mnoc";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		};

		port@1 {
		reg = <1>;
		};

		port@2 {
		reg = <2>;
		};

		port@3 {
		reg = <3>;
		};

		port@4 {
		reg = <4>;
		};

		port@5 {
		reg = <5>;
		};
		};
		};

		camcc: clock-controller@ad00000 {