Commit 3d8d35bf authored by Simona Vetter's avatar Simona Vetter
Browse files

Merge tag 'drm-msm-fixes-2025-10-29' of https://gitlab.freedesktop.org/drm/msm into drm-fixes



Fixes for v6.18-rc4

CI
- Disable broken sanity job

GEM
- Fix vm_bind prealloc error path
- Fix dma-buf import free
- Fix last-fence update
- Reject MAP_NULL if PRR is unsupported
- Ensure vm is created in VM_BIND ioctl

GPU
- GMU fw parsing fix

DPU:
- Fixed mode_valid callback
- Fixed planes on DPU 1.x devices.

Signed-off-by: default avatarSimona Vetter <simona.vetter@ffwll.ch>
From: Rob Clark <rob.clark@oss.qualcomm.com>
Link: https://patch.msgid.link/CACSVV03kUm1ms7FBg0m9U4ZcyickSWbnayAWqYqs0XH4UjWf+A@mail.gmail.com
parents 3a9f6bd5 f5d07956
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+1 −1
Original line number Diff line number Diff line
@@ -280,7 +280,7 @@ sanity:
    GIT_STRATEGY: none
  script:
    # ci-fairy check-commits --junit-xml=check-commits.xml
    - ci-fairy check-merge-request --require-allow-collaboration --junit-xml=check-merge-request.xml
    # - ci-fairy check-merge-request --require-allow-collaboration --junit-xml=check-merge-request.xml
    - |
      set -eu
      image_tags=(
+4 −1
Original line number Diff line number Diff line
@@ -780,6 +780,9 @@ static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk)
	return true;
}

#define NEXT_BLK(blk) \
	((const struct block_header *)((const char *)(blk) + sizeof(*(blk)) + (blk)->size))

static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu)
{
	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
@@ -811,7 +814,7 @@ static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu)

	for (blk = (const struct block_header *) fw_image->data;
	     (const u8*) blk < fw_image->data + fw_image->size;
	     blk = (const struct block_header *) &blk->data[blk->size >> 2]) {
	     blk = NEXT_BLK(blk)) {
		if (blk->size == 0)
			continue;

+0 −7
Original line number Diff line number Diff line
@@ -348,13 +348,6 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags,
	return 0;
}

static bool
adreno_smmu_has_prr(struct msm_gpu *gpu)
{
	struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(&gpu->pdev->dev);
	return adreno_smmu && adreno_smmu->set_prr_addr;
}

int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx,
		     uint32_t param, uint64_t *value, uint32_t *len)
{
+3 −0
Original line number Diff line number Diff line
@@ -1545,6 +1545,9 @@ static enum drm_mode_status dpu_crtc_mode_valid(struct drm_crtc *crtc,
	adjusted_mode_clk = dpu_core_perf_adjusted_mode_clk(mode->clock,
							    dpu_kms->perf.perf_cfg);

	if (dpu_kms->catalog->caps->has_3d_merge)
		adjusted_mode_clk /= 2;

	/*
	 * The given mode, adjusted for the perf clock factor, should not exceed
	 * the max core clock rate
+2 −2
Original line number Diff line number Diff line
@@ -267,8 +267,8 @@ static const u32 wb2_formats_rgb_yuv[] = {
		.base = 0x200, .len = 0xa0,}, \
	.csc_blk = {.name = "csc", \
		.base = 0x320, .len = 0x100,}, \
	.format_list = plane_formats_yuv, \
	.num_formats = ARRAY_SIZE(plane_formats_yuv), \
	.format_list = plane_formats, \
	.num_formats = ARRAY_SIZE(plane_formats), \
	.rotation_cfg = NULL, \
	}

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