Commit 3de96d81 authored by Christian Marangi's avatar Christian Marangi Committed by Thomas Bogendoerfer
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dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property



Document brcm,bmips-cbr-reg property.

Some SoC suffer from a BUG where CBR(Core Base Register)
address might be badly or never initialized by the Bootloader
or reading it from co-processor registers, if the system boots
from secondary CPU, results in invalid address.

The CBR address is always the same on the SoC.

Usage of this property is to give an address also in these broken
configuration/bootloader.

Signed-off-by: default avatarChristian Marangi <ansuelsmth@gmail.com>
Acked-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Acked-by: default avatarFlorian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent a5c05453
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Original line number Diff line number Diff line
@@ -55,6 +55,16 @@ properties:
         under the "cpus" node.
        $ref: /schemas/types.yaml#/definitions/uint32

      brcm,bmips-cbr-reg:
        description: Reference address of the CBR.
          Some SoC suffer from a BUG where CBR(Core Base Register)
          address might be badly or never initialized by the Bootloader
          or reading it from co-processor registers, if the system boots
          from secondary CPU, results in invalid address.
          The CBR address is always the same on the SoC hence it
          can be provided in DT to handle these broken case.
        $ref: /schemas/types.yaml#/definitions/uint32

    patternProperties:
      "^cpu@[0-9]$":
        type: object
@@ -64,6 +74,20 @@ properties:
    required:
      - mips-hpt-frequency

if:
  properties:
    compatible:
      contains:
        enum:
          - brcm,bcm6358
          - brcm,bcm6368

then:
  properties:
    cpus:
      required:
        - brcm,bmips-cbr-reg

additionalProperties: true

examples: