Commit 40bae1ae authored by Karthi Kandasamy's avatar Karthi Kandasamy Committed by Alex Deucher
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drm/amd/display: Move mcache allocation programming from DML to resource 



[Why]
mcache allocation programming is not part of DML's core responsibilities.
Keeping this logic in DML leads to poor separation of concerns and complicates maintenance.

[How]
Refactored code to move mcache parameter preparation and mcache ID assignment
into the resource file.

Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Signed-off-by: default avatarKarthi Kandasamy <karthi.kandasamy@amd.com>
Signed-off-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 17accf4f

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+9 −0
Original line number Diff line number Diff line
@@ -5525,6 +5525,14 @@ struct dscl_prog_data *resource_get_dscl_prog_data(struct pipe_ctx *pipe_ctx) 
	return &pipe_ctx->plane_res.scl_data.dscl_prog_data;

}



static bool resource_allocate_mcache(struct dc_state *context, const struct  dc_mcache_params *mcache_params)

{

	if (context->clk_mgr->ctx->dc->res_pool->funcs->program_mcache_pipe_config)

		context->clk_mgr->ctx->dc->res_pool->funcs->program_mcache_pipe_config(context, mcache_params);



	return true;

}



void resource_init_common_dml2_callbacks(struct dc *dc, struct dml2_configuration_options *dml2_options)

{

	dml2_options->callbacks.dc = dc;
@@ -5544,6 +5552,7 @@ void resource_init_common_dml2_callbacks(struct dc *dc, struct dml2_configuratio 
	dml2_options->callbacks.get_stream_status = &dc_state_get_stream_status;

	dml2_options->callbacks.get_stream_from_id = &dc_state_get_stream_from_id;

	dml2_options->callbacks.get_max_flickerless_instant_vtotal_increase = &dc_stream_get_max_flickerless_instant_vtotal_increase;

	dml2_options->callbacks.allocate_mcache = &resource_allocate_mcache;



	dml2_options->svp_pstate.callbacks.dc = dc;

	dml2_options->svp_pstate.callbacks.add_phantom_plane = &dc_state_add_phantom_plane;

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

+1 −1
Original line number Diff line number Diff line
@@ -952,7 +952,7 @@ static unsigned int map_stream_to_dml21_display_cfg(const struct dml2_context *d 
	return location;

}



static unsigned int map_plane_to_dml21_display_cfg(const struct dml2_context *dml_ctx, unsigned int stream_id,

unsigned int map_plane_to_dml21_display_cfg(const struct dml2_context *dml_ctx, unsigned int stream_id,

		const struct dc_plane_state *plane, const struct dc_state *context)

{

	unsigned int plane_id;

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.h

+2 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ struct dc_state; 
struct dcn_watermarks;

union dcn_watermark_set;

struct pipe_ctx;

struct dc_plane_state;



struct dml2_context;

struct dml2_configuration_options;
@@ -25,4 +26,5 @@ void dml21_extract_watermark_sets(const struct dc *in_dc, union dcn_watermark_se 
void dml21_map_hw_resources(struct dml2_context *dml_ctx);

void dml21_get_pipe_mcache_config(struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog, struct dml2_pipe_configuration_descriptor *mcache_pipe_config);

void dml21_set_dc_p_state_type(struct pipe_ctx *pipe_ctx, struct dml2_per_stream_programming *stream_programming, bool sub_vp_enabled);

unsigned int map_plane_to_dml21_display_cfg(const struct dml2_context *dml_ctx, unsigned int stream_id, const struct dc_plane_state *plane, const struct dc_state *context);

#endif

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

+40 −0
Original line number Diff line number Diff line
@@ -12,6 +12,8 @@ 
#include "dml21_translation_helper.h"

#include "dml2_dc_resource_mgmt.h"



#define INVALID -1



static bool dml21_allocate_memory(struct dml2_context **dml_ctx)

{

	*dml_ctx = vzalloc(sizeof(struct dml2_context));
@@ -208,10 +210,40 @@ static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_sta 
	}

}



static void dml21_prepare_mcache_params(struct dml2_context *dml_ctx, struct dc_state *context, struct dc_mcache_params *mcache_params)

{

	int dc_plane_idx = 0;

	int dml_prog_idx, stream_idx, plane_idx;

	struct dml2_per_plane_programming *pln_prog = NULL;



	for (stream_idx = 0; stream_idx < context->stream_count; stream_idx++) {

		for (plane_idx = 0; plane_idx < context->stream_status[stream_idx].plane_count; plane_idx++) {

			dml_prog_idx = map_plane_to_dml21_display_cfg(dml_ctx, context->streams[stream_idx]->stream_id, context->stream_status[stream_idx].plane_states[plane_idx], context);

			if (dml_prog_idx == INVALID) {

				continue;

			}

			pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx];

			mcache_params[dc_plane_idx].valid = pln_prog->mcache_allocation.valid;

			mcache_params[dc_plane_idx].num_mcaches_plane0 = pln_prog->mcache_allocation.num_mcaches_plane0;

			mcache_params[dc_plane_idx].num_mcaches_plane1 = pln_prog->mcache_allocation.num_mcaches_plane1;

			mcache_params[dc_plane_idx].requires_dedicated_mall_mcache = pln_prog->mcache_allocation.requires_dedicated_mall_mcache;

			mcache_params[dc_plane_idx].last_slice_sharing.plane0_plane1 = pln_prog->mcache_allocation.last_slice_sharing.plane0_plane1;

			memcpy(mcache_params[dc_plane_idx].mcache_x_offsets_plane0,

				pln_prog->mcache_allocation.mcache_x_offsets_plane0,

				sizeof(int) * (DML2_MAX_MCACHES + 1));

			memcpy(mcache_params[dc_plane_idx].mcache_x_offsets_plane1,

				pln_prog->mcache_allocation.mcache_x_offsets_plane1,

				sizeof(int) * (DML2_MAX_MCACHES + 1));

			dc_plane_idx++;

		}

	}

}



static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)

{

	bool result = false;

	struct dml2_build_mode_programming_in_out *mode_programming = &dml_ctx->v21.mode_programming;

	struct dc_mcache_params mcache_params[MAX_PLANES] = {0};



	memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg));

	memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping));
@@ -246,6 +278,14 @@ static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_s 
		dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, in_dc->current_state);

		/* if subvp phantoms are present, expand them into dc context */

		dml21_handle_phantom_streams_planes(in_dc, context, dml_ctx);



		if (in_dc->res_pool->funcs->program_mcache_pipe_config) {

			//Prepare mcache params for each plane based on mcache output from DML

			dml21_prepare_mcache_params(dml_ctx, context, mcache_params);



			//populate mcache regs to each pipe

			dml_ctx->config.callbacks.allocate_mcache(context, mcache_params);

		}

	}



	/* Copy DML CLK, WM and REG outputs to bandwidth context */

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h

+64 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 


#include "os_types.h"

#include "dml_top_soc_parameter_types.h"

#include "dml_top_display_cfg_types.h"



struct dc;

struct dc_state;
@@ -65,4 +66,67 @@ struct socbb_ip_params_external { 
	struct dml2_ip_capabilities ip_params;

	struct dml2_soc_bb soc_bb;

};



/*mcache parameters decided by dml*/

struct dc_mcache_params {

	bool valid;

	/*

	* For iMALL, dedicated mall mcaches are required (sharing of last

	* slice possible), for legacy phantom or phantom without return

	* the only mall mcaches need to be valid.

	*/

	bool requires_dedicated_mall_mcache;

	unsigned int num_mcaches_plane0;

	unsigned int num_mcaches_plane1;

	/*

	* Generally, plane0/1 slices must use a disjoint set of caches

	* but in some cases the final segement of the two planes can

	* use the same cache. If plane0_plane1 is set, then this is

	* allowed.

	*

	* Similarly, the caches allocated to MALL prefetcher are generally

	* disjoint, but if mall_prefetch is set, then the final segment

	* between the main and the mall pixel requestor can use the same

	* cache.

	*

	* Note that both bits may be set at the same time.

	*/

	struct {

		bool mall_comb_mcache_p0;

		bool mall_comb_mcache_p1;

		bool plane0_plane1;

	} last_slice_sharing;

	/*

	* A plane is divided into vertical slices of mcaches,

	* which wrap on the surface width.

	*

	* For example, if the surface width is 7680, and split into

	* three slices of equal width, the boundary array would contain

	* [2560, 5120, 7680]

	*

	* The assignments are

	* 0 = [0 .. 2559]

	* 1 = [2560 .. 5119]

	* 2 = [5120 .. 7679]

	* 0 = [7680 .. INF]

	* The final element implicitly is the same as the first, and

	* at first seems invalid since it is never referenced (since)

	* it is outside the surface. However, its useful when shifting

	* (see below).

	*

	* For any given valid mcache assignment, a shifted version, wrapped

	* on the surface width boundary is also assumed to be valid.

	*

	* For example, shifting [2560, 5120, 7680] by -50 results in

	* [2510, 5170, 7630].

	*

	* The assignments are now:

	* 0 = [0 .. 2509]

	* 1 = [2510 .. 5169]

	* 2 = [5170 .. 7629]

	* 0 = [7630 .. INF]

	*/

	int mcache_x_offsets_plane0[DML2_MAX_MCACHES + 1];

	int mcache_x_offsets_plane1[DML2_MAX_MCACHES + 1];

};

#endif