Commit 41056416 authored by Dmitry Rokosov's avatar Dmitry Rokosov Committed by Jerome Brunet
Browse files

dt-bindings: clock: meson: a1: peripherals: support sys_pll input 



The 'sys_pll' input is an optional clock that can be used to generate
'sys_pll_div16', which serves as one of the sources for the GEN clock.

Signed-off-by: default avatarDmitry Rokosov <ddrokosov@salutedevices.com>
Acked-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240515185103.20256-5-ddrokosov@salutedevices.com


Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 96f3b978

Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml

+7 −2
Original line number Diff line number Diff line
@@ -30,6 +30,8 @@ properties: 
      - description: input fixed pll div7

      - description: input hifi pll

      - description: input oscillator (usually at 24MHz)

      - description: input sys pll

    minItems: 6 # sys_pll is optional



  clock-names:

    items:
@@ -39,6 +41,8 @@ properties: 
      - const: fclk_div7

      - const: hifi_pll

      - const: xtal

      - const: sys_pll

    minItems: 6 # sys_pll is optional



required:

  - compatible
@@ -65,9 +69,10 @@ examples: 
                     <&clkc_pll CLKID_FCLK_DIV5>,

                     <&clkc_pll CLKID_FCLK_DIV7>,

                     <&clkc_pll CLKID_HIFI_PLL>,

                     <&xtal>;

                     <&xtal>,

                     <&clkc_pll CLKID_SYS_PLL>;

            clock-names = "fclk_div2", "fclk_div3",

                          "fclk_div5", "fclk_div7",

                          "hifi_pll", "xtal";

                          "hifi_pll", "xtal", "sys_pll";

        };

    };

include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h

+1 −0
Original line number Diff line number Diff line
@@ -164,5 +164,6 @@ 
#define CLKID_DMC_SEL		151

#define CLKID_DMC_DIV		152

#define CLKID_DMC_SEL2		153

#define CLKID_SYS_PLL_DIV16	154



#endif /* __A1_PERIPHERALS_CLKC_H */