Unverified Commit cb51bfee authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge patch series "riscv: hwprobe: add Zicond, Zacas and Ztso support" 

Clément Léger <cleger@rivosinc.com> says:

This series add support for a few more extensions that are present in
the RVA22U64/RVA23U64 (either mandatory or optional) and that are useful
for userspace:
- Zicond
- Zacas
- Ztso

Series currently based on riscv/for-next.

* b4-shazam-lts:
  riscv: hwprobe: export Zicond extension
  riscv: hwprobe: export Zacas ISA extension
  riscv: add ISA extension parsing for Zacas
  dt-bindings: riscv: add Zacas ISA extension description
  riscv: hwprobe: export Ztso ISA extension
  riscv: add ISA extension parsing for Ztso

Link: https://lore.kernel.org/r/20231220155723.684081-1-cleger@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents 62694797 3359866b

Documentation/arch/riscv/hwprobe.rst

+13 −0
Original line number Diff line number Diff line
@@ -175,6 +175,19 @@ The following keys are defined: 
       defined in the RISC-V ISA manual starting from commit 056b6ff467c7

       ("Zfa is ratified").



  * :c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Ztso extension is supported as

       defined in the RISC-V ISA manual starting from commit 5618fb5a216b

       ("Ztso is now ratified.")



  * :c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Zacas extension is supported as

       defined in the Atomic Compare-and-Swap (CAS) instructions manual starting

       from commit 5059e0ca641c ("update to ratified").



  * :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as

       defined in the RISC-V Integer Conditional (Zicond) operations extension

       manual starting from commit 95cf1f9 ("Add changes requested by Ved

       during signoff")



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance

  information about the selected set of processors.

Documentation/devicetree/bindings/riscv/extensions.yaml

+6 −0
Original line number Diff line number Diff line
@@ -171,6 +171,12 @@ properties: 
            memory types as ratified in the 20191213 version of the privileged

            ISA specification.



        - const: zacas

          description: |

            The Zacas extension for Atomic Compare-and-Swap (CAS) instructions

            is supported as ratified at commit 5059e0ca641c ("update to

            ratified") of the riscv-zacas.



        - const: zba

          description: |

            The standard Zba bit-manipulation extension for address generation

arch/riscv/include/asm/hwcap.h

+2 −0
Original line number Diff line number Diff line
@@ -78,6 +78,8 @@ 
#define RISCV_ISA_EXT_ZVFH		69

#define RISCV_ISA_EXT_ZVFHMIN		70

#define RISCV_ISA_EXT_ZFA		71

#define RISCV_ISA_EXT_ZTSO		72

#define RISCV_ISA_EXT_ZACAS		73



#define RISCV_ISA_EXT_MAX		128

#define RISCV_ISA_EXT_INVALID		U32_MAX

arch/riscv/include/uapi/asm/hwprobe.h

+3 −0
Original line number Diff line number Diff line
@@ -56,6 +56,9 @@ struct riscv_hwprobe { 
#define		RISCV_HWPROBE_EXT_ZVFH		(1 << 30)

#define		RISCV_HWPROBE_EXT_ZVFHMIN	(1 << 31)

#define		RISCV_HWPROBE_EXT_ZFA		(1ULL << 32)

#define		RISCV_HWPROBE_EXT_ZTSO		(1ULL << 33)

#define		RISCV_HWPROBE_EXT_ZACAS		(1ULL << 34)

#define		RISCV_HWPROBE_EXT_ZICOND	(1ULL << 35)

#define RISCV_HWPROBE_KEY_CPUPERF_0	5

#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)

#define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)

arch/riscv/kernel/cpufeature.c

+2 −0
Original line number Diff line number Diff line
@@ -255,6 +255,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { 
	__RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL),

	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),

	__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),

	__RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),

	__RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),

	__RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),

	__RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
@@ -275,6 +276,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { 
	__RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT),

	__RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED),

	__RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH),

	__RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),

	__RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),

	__RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),

	__RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),