Commit 47271a0c authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.15-2025-04-09' of... 

Merge tag 'amd-drm-fixes-6.15-2025-04-09' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.15-2025-04-09:

amdgpu:
- MES FW version caching fixes
- Only use GTT as a fallback if we already have a backing store
- dma_buf fix
- IP discovery fix
- Replay and PSR with VRR fix
- DC FP fixes
- eDP fixes
- KIQ TLB invalidate fix
- Enable dmem groups support
- Allow pinning VRAM dma bufs if imports can do P2P
- Workload profile fixes
- Prevent possible division by 0 in fan handling

amdkfd:
- Queue reset fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://lore.kernel.org/r/20250409165238.1180153-1-alexander.deucher@amd.com
parents 9afaa16c 34779e14

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+0 −1
Original line number Diff line number Diff line
@@ -353,7 +353,6 @@ enum amdgpu_kiq_irq { 
	AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,

	AMDGPU_CP_KIQ_IRQ_LAST

};

#define SRIOV_USEC_TIMEOUT  1200000 /* wait 12 * 100ms for SRIOV */

#define MAX_KIQ_REG_WAIT       5000 /* in usecs, 5ms */

#define MAX_KIQ_REG_BAILOUT_INTERVAL   5 /* in msecs, 5ms */

#define MAX_KIQ_REG_TRY 1000

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+7 −0
Original line number Diff line number Diff line
@@ -3643,6 +3643,13 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) 
			    adev, adev->ip_blocks[i].version->type))

			continue;



		/* Since we skip suspend for S0i3, we need to cancel the delayed

		 * idle work here as the suspend callback never gets called.

		 */

		if (adev->in_s0ix &&

		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX &&

		    amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 0, 0))

			cancel_delayed_work_sync(&adev->gfx.idle_work);

		/* skip suspend of gfx/mes and psp for S0ix

		 * gfx is in gfxoff state, so on resume it will exit gfxoff just

		 * like at runtime. PSP is also part of the always on hardware

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

+2 −0
Original line number Diff line number Diff line
@@ -120,6 +120,8 @@ MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin"); 
MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin");

MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin");

MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin");

MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin");

MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin");



#define mmIP_DISCOVERY_VERSION  0x16A00

#define mmRCC_CONFIG_MEMSIZE	0xde3

drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c

+19 −8
Original line number Diff line number Diff line
@@ -75,11 +75,25 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, 
 */

static int amdgpu_dma_buf_pin(struct dma_buf_attachment *attach)

{

	struct drm_gem_object *obj = attach->dmabuf->priv;

	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);

	struct dma_buf *dmabuf = attach->dmabuf;

	struct amdgpu_bo *bo = gem_to_amdgpu_bo(dmabuf->priv);

	u32 domains = bo->preferred_domains;



	dma_resv_assert_held(dmabuf->resv);



	/*

	 * Try pinning into VRAM to allow P2P with RDMA NICs without ODP

	 * support if all attachments can do P2P. If any attachment can't do

	 * P2P just pin into GTT instead.

	 */

	list_for_each_entry(attach, &dmabuf->attachments, node)

		if (!attach->peer2peer)

			domains &= ~AMDGPU_GEM_DOMAIN_VRAM;



	if (domains & AMDGPU_GEM_DOMAIN_VRAM)

		bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;



	/* pin buffer into GTT */

	return amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);

	return amdgpu_bo_pin(bo, domains);

}



/**
@@ -134,9 +148,6 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach, 
		r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);

		if (r)

			return ERR_PTR(r);



	} else if (bo->tbo.resource->mem_type != TTM_PL_TT) {

		return ERR_PTR(-EBUSY);

	}



	switch (bo->tbo.resource->mem_type) {
@@ -184,7 +195,7 @@ static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach, 
				 struct sg_table *sgt,

				 enum dma_data_direction dir)

{

	if (sgt->sgl->page_link) {

	if (sg_page(sgt->sgl)) {

		dma_unmap_sgtable(attach->dev, sgt, dir, 0);

		sg_free_table(sgt);

		kfree(sgt);

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

+14 −5
Original line number Diff line number Diff line
@@ -699,12 +699,10 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, 
				   uint32_t flush_type, bool all_hub,

				   uint32_t inst)

{

	u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT :

		adev->usec_timeout;

	struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring;

	struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];

	unsigned int ndw;

	int r;

	int r, cnt = 0;

	uint32_t seq;



	/*
@@ -761,10 +759,21 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, 


		amdgpu_ring_commit(ring);

		spin_unlock(&adev->gfx.kiq[inst].ring_lock);

		if (amdgpu_fence_wait_polling(ring, seq, usec_timeout) < 1) {



		r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);



		might_sleep();

		while (r < 1 && cnt++ < MAX_KIQ_REG_TRY &&

		       !amdgpu_reset_pending(adev->reset_domain)) {

			msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);

			r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);

		}



		if (cnt > MAX_KIQ_REG_TRY) {

			dev_err(adev->dev, "timeout waiting for kiq fence\n");

			r = -ETIME;

		}

		} else

			r = 0;

	}



error_unlock_reset: