Merge tag 'tegra-for-5.14-dt-bindings' of...

    additionalProperties: false

  core-domain:

    type: object

    description: |

      The vast majority of hardware blocks of Tegra SoC belong to a

      Core power domain, which has a dedicated voltage rail that powers

      the blocks.

    properties:

      operating-points-v2:

        description:

          Should contain level, voltages and opp-supported-hw property.

          The supported-hw is a bitfield indicating SoC speedo or process

          ID mask.

      "#power-domain-cells":

        const: 0

    required:

      - operating-points-v2

      - "#power-domain-cells"

    additionalProperties: false

  core-supply:

    description:

      Phandle to voltage regulator connected to the SoC Core power rail.

required:

  - compatible

  - reg

    tegra_pmc: pmc@7000e400 {

              compatible = "nvidia,tegra210-pmc";

              reg = <0x7000e400 0x400>;

              core-supply = <&regulator>;

              clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;

              clock-names = "pclk", "clk32k_in";

              #clock-cells = <1>;

              nvidia,core-power-req-active-high;

              nvidia,sys-clock-req-active-high;

              pd_core: core-domain {

                      operating-points-v2 = <&core_opp_table>;

                      #power-domain-cells = <0>;

              };

              powergates {

                    pd_audio: aud {

                            clocks = <&tegra_car TEGRA210_CLK_APE>,

                                     <&tegra_car TEGRA210_CLK_APB2APE>;

                            resets = <&tegra_car 198>;

                            power-domains = <&pd_core>;

                            #power-domain-cells = <0>;

                    };

                    pd_xusbss: xusba {

                            clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;

                            resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;

                            power-domains = <&pd_core>;

                            #power-domain-cells = <0>;

                    };

              };

NVIDIA Tegra114 Clock And Reset Controller

This binding uses the common clock binding:

Documentation/devicetree/bindings/clock/clock-bindings.txt

The CAR (Clock And Reset) Controller on Tegra is the HW module responsible

for muxing and gating Tegra's clocks, and setting their rates.

Required properties :

- compatible : Should be "nvidia,tegra114-car"

- reg : Should contain CAR registers location and length

- clocks : Should contain phandle and clock specifiers for two clocks:

  the 32 KHz "32k_in", and the board-specific oscillator "osc".

- #clock-cells : Should be 1.

  In clock consumers, this cell represents the clock ID exposed by the

  CAR. The assignments may be found in header file

  <dt-bindings/clock/tegra114-car.h>.

- #reset-cells : Should be 1.

  In clock consumers, this cell represents the bit number in the CAR's

  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.

Example SoC include file:

/ {

	tegra_car: clock {

		compatible = "nvidia,tegra114-car";

		reg = <0x60006000 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

	usb@c5004000 {

		clocks = <&tegra_car TEGRA114_CLK_USB2>;

	};

};

Example board file:

/ {

	clocks {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <0>;

		osc: clock@0 {

			compatible = "fixed-clock";

			reg = <0>;

			#clock-cells = <0>;

			clock-frequency = <12000000>;

		};

		clk_32k: clock@1 {

			compatible = "fixed-clock";

			reg = <1>;

			#clock-cells = <0>;

			clock-frequency = <32768>;

		};

	};

	&tegra_car {

		clocks = <&clk_32k> <&osc>;

	};

};

NVIDIA Tegra124 and Tegra132 Clock And Reset Controller

This binding uses the common clock binding:

Documentation/devicetree/bindings/clock/clock-bindings.txt

The CAR (Clock And Reset) Controller on Tegra is the HW module responsible

for muxing and gating Tegra's clocks, and setting their rates.

Required properties :

- compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"

- reg : Should contain CAR registers location and length

- clocks : Should contain phandle and clock specifiers for two clocks:

  the 32 KHz "32k_in", and the board-specific oscillator "osc".

- #clock-cells : Should be 1.

  In clock consumers, this cell represents the clock ID exposed by the

  CAR. The assignments may be found in the header files

  <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common

  to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>

  (for Tegra124-specific clocks).

- #reset-cells : Should be 1.

  In clock consumers, this cell represents the bit number in the CAR's

  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.

- nvidia,external-memory-controller : phandle of the EMC driver.

The node should contain a "emc-timings" subnode for each supported RAM type (see

field RAM_CODE in register PMC_STRAPPING_OPT_A).

Required properties for "emc-timings" nodes :

- nvidia,ram-code : Should contain the value of RAM_CODE this timing set

  is used for.

Each "emc-timings" node should contain a "timing" subnode for every supported

EMC clock rate.

Required properties for "timing" nodes :

- clock-frequency : Should contain the memory clock rate to which this timing

relates.

- nvidia,parent-clock-frequency : Should contain the rate at which the current

parent of the EMC clock should be running at this timing.

- clocks : Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names : Must include the following entries:

  - emc-parent : the clock that should be the parent of the EMC clock at this

timing.

Example SoC include file:

/ {

	tegra_car: clock@60006000 {

		compatible = "nvidia,tegra124-car";

		reg = <0x60006000 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

		nvidia,external-memory-controller = <&emc>;

	};

	usb@c5004000 {

		clocks = <&tegra_car TEGRA124_CLK_USB2>;

	};

};

Example board file:

/ {

	clocks {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <0>;

		osc: clock@0 {

			compatible = "fixed-clock";

			reg = <0>;

			#clock-cells = <0>;

			clock-frequency = <112400000>;

		};

		clk_32k: clock@1 {

			compatible = "fixed-clock";

			reg = <1>;

			#clock-cells = <0>;

			clock-frequency = <32768>;

		};

	};

	&tegra_car {

		clocks = <&clk_32k> <&osc>;

	};

	clock@60006000 {

		emc-timings-3 {

			nvidia,ram-code = <3>;

			timing-12750000 {

				clock-frequency = <12750000>;

				nvidia,parent-clock-frequency = <408000000>;

				clocks = <&tegra_car TEGRA124_CLK_PLL_P>;

				clock-names = "emc-parent";

			};

			timing-20400000 {

				clock-frequency = <20400000>;

				nvidia,parent-clock-frequency = <408000000>;

				clocks = <&tegra_car TEGRA124_CLK_PLL_P>;

				clock-names = "emc-parent";

			};

		};

	};

};

# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra Clock and Reset Controller

maintainers:

  - Jon Hunter <jonathanh@nvidia.com>

  - Thierry Reding <thierry.reding@gmail.com>

description: |

  The Clock and Reset (CAR) is the HW module responsible for muxing and gating

  Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.

  CLKGEN provides the registers to program the PLLs. It controls most of

  the clock source programming and most of the clock dividers.

  CLKGEN input signals include the external clock for the reference frequency

  (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).

  Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.

  RSTGEN provides the registers needed to control resetting of each block in

  the Tegra system.

properties:

  compatible:

    const: nvidia,tegra124-car

  reg:

    maxItems: 1

  '#clock-cells':

    const: 1

  "#reset-cells":

    const: 1

  nvidia,external-memory-controller:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      phandle of the external memory controller node

patternProperties:

  "^emc-timings-[0-9]+$":

    type: object

    properties:

      nvidia,ram-code:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that

          this timing set is used for

    patternProperties:

      "^timing-[0-9]+$":

        type: object

        properties:

          clock-frequency:

            description:

              external memory clock rate in Hz

            minimum: 1000000

            maximum: 1000000000

          nvidia,parent-clock-frequency:

            $ref: /schemas/types.yaml#/definitions/uint32

            description:

              rate of parent clock in Hz

            minimum: 1000000

            maximum: 1000000000

          clocks:

            items:

              - description: parent clock of EMC

          clock-names:

            items:

              - const: emc-parent

        required:

          - clock-frequency

          - nvidia,parent-clock-frequency

          - clocks

          - clock-names

        additionalProperties: false

    additionalProperties: false

required:

  - compatible

  - reg

  - '#clock-cells'

  - "#reset-cells"

additionalProperties: false

examples:

  - |

    #include <dt-bindings/clock/tegra124-car.h>

    car: clock-controller@60006000 {

        compatible = "nvidia,tegra124-car";

        reg = <0x60006000 0x1000>;

        #clock-cells = <1>;

        #reset-cells = <1>;

    };

    usb-controller@c5004000 {

        compatible = "nvidia,tegra20-ehci";

        reg = <0xc5004000 0x4000>;

        clocks = <&car TEGRA124_CLK_USB2>;

        resets = <&car TEGRA124_CLK_USB2>;

    };

NVIDIA Tegra20 Clock And Reset Controller

This binding uses the common clock binding:

Documentation/devicetree/bindings/clock/clock-bindings.txt

The CAR (Clock And Reset) Controller on Tegra is the HW module responsible

for muxing and gating Tegra's clocks, and setting their rates.

Required properties :

- compatible : Should be "nvidia,tegra20-car"

- reg : Should contain CAR registers location and length

- clocks : Should contain phandle and clock specifiers for two clocks:

  the 32 KHz "32k_in", and the board-specific oscillator "osc".

- #clock-cells : Should be 1.

  In clock consumers, this cell represents the clock ID exposed by the

  CAR. The assignments may be found in header file

  <dt-bindings/clock/tegra20-car.h>.

- #reset-cells : Should be 1.

  In clock consumers, this cell represents the bit number in the CAR's

  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.

Example SoC include file:

/ {

	tegra_car: clock {

		compatible = "nvidia,tegra20-car";

		reg = <0x60006000 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

	usb@c5004000 {

		clocks = <&tegra_car TEGRA20_CLK_USB2>;

	};

};

Example board file:

/ {

	clocks {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <0>;

		osc: clock@0 {

			compatible = "fixed-clock";

			reg = <0>;

			#clock-cells = <0>;

			clock-frequency = <12000000>;

		};

		clk_32k: clock@1 {

			compatible = "fixed-clock";

			reg = <1>;

			#clock-cells = <0>;

			clock-frequency = <32768>;

		};

	};

	&tegra_car {

		clocks = <&clk_32k> <&osc>;

	};

};