Commit 480b3153 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/linkup-fix' 

- Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to PCIE_RESET_CONFIG_WAIT_MS (the
  required delay before sending config requests after a reset) (Niklas
  Cassel)

- PCIE_T_RRS_READY_MS and PCIE_RESET_CONFIG_WAIT_MS were two names for the
  same delay; replace PCIE_T_RRS_READY_MS with PCIE_RESET_CONFIG_WAIT_MS
  and remove PCIE_T_RRS_READY_MS (Niklas Cassel)

- Add required PCIE_RESET_CONFIG_WAIT_MS delay after Link up IRQ to
  dw-rockchip, qcom (Niklas Cassel)

- Add required PCIE_RESET_CONFIG_WAIT_MS after waiting for Link up on
  Ports that support > 5.0 GT/s in dwc core (Niklas Cassel)

- Move LINK_WAIT_SLEEP_MS and LINK_WAIT_MAX_RETRIES to pci.h and prefix
  with 'PCIE_' for potential sharing across drivers (Niklas Cassel)

* pci/controller/linkup-fix:
  PCI: Move link up wait time and max retries macros to pci.h
  PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up
  PCI: qcom: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ
  PCI: dw-rockchip: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ
  PCI: rockchip-host: Use macro PCIE_RESET_CONFIG_WAIT_MS
  PCI: Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to PCIE_RESET_CONFIG_WAIT_MS
parents 769ce531 d7467bc7

drivers/pci/controller/dwc/pcie-designware.c

+11 −3
Original line number Diff line number Diff line
@@ -702,18 +702,26 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) 
	int retries;



	/* Check if the link is up or not */

	for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {

	for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {

		if (dw_pcie_link_up(pci))

			break;



		msleep(LINK_WAIT_SLEEP_MS);

		msleep(PCIE_LINK_WAIT_SLEEP_MS);

	}



	if (retries >= LINK_WAIT_MAX_RETRIES) {

	if (retries >= PCIE_LINK_WAIT_MAX_RETRIES) {

		dev_info(pci->dev, "Phy link never came up\n");

		return -ETIMEDOUT;

	}



	/*

	 * As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link

	 * speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms

	 * after Link training completes before sending a Configuration Request.

	 */

	if (pci->max_link_speed > 2)

		msleep(PCIE_RESET_CONFIG_WAIT_MS);



	offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);

	val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);

drivers/pci/controller/dwc/pcie-designware.h

+0 −4
Original line number Diff line number Diff line
@@ -62,10 +62,6 @@ 
#define dw_pcie_cap_set(_pci, _cap) \

	set_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps)



/* Parameters for the waiting for link up routine */

#define LINK_WAIT_MAX_RETRIES		10

#define LINK_WAIT_SLEEP_MS		90



/* Parameters for the waiting for iATU enabled routine */

#define LINK_WAIT_MAX_IATU_RETRIES	5

#define LINK_WAIT_IATU			9

drivers/pci/controller/dwc/pcie-dw-rockchip.c

+1 −0
Original line number Diff line number Diff line
@@ -458,6 +458,7 @@ static irqreturn_t rockchip_pcie_rc_sys_irq_thread(int irq, void *arg) 


	if (reg & PCIE_RDLH_LINK_UP_CHGED) {

		if (rockchip_pcie_link_up(pci)) {

			msleep(PCIE_RESET_CONFIG_WAIT_MS);

			dev_dbg(dev, "Received Link up event. Starting enumeration!\n");

			/* Rescan the bus to enumerate endpoint devices */

			pci_lock_rescan_remove();

drivers/pci/controller/dwc/pcie-qcom.c

+1 −0
Original line number Diff line number Diff line
@@ -1564,6 +1564,7 @@ static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data) 
	writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR);



	if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) {

		msleep(PCIE_RESET_CONFIG_WAIT_MS);

		dev_dbg(dev, "Received Link up event. Starting enumeration!\n");

		/* Rescan the bus to enumerate endpoint devices */

		pci_lock_rescan_remove();

drivers/pci/controller/pcie-rockchip-host.c

+1 −1
Original line number Diff line number Diff line
@@ -325,7 +325,7 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) 
	msleep(PCIE_T_PVPERL_MS);

	gpiod_set_value_cansleep(rockchip->perst_gpio, 1);



	msleep(PCIE_T_RRS_READY_MS);

	msleep(PCIE_RESET_CONFIG_WAIT_MS);



	/* 500ms timeout value should be enough for Gen1/2 training */

	err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,