Commit d7467bc7 authored by Niklas Cassel's avatar Niklas Cassel Committed by Manivannan Sadhasivam
Browse files

PCI: Move link up wait time and max retries macros to pci.h 



Move the LINK_WAIT_SLEEP_MS and LINK_WAIT_MAX_RETRIES macros to pci.h.
Prefix the macros with PCIE_ in order to avoid redefining these for
drivers that already have macros named like this.

No functional changes.

Suggested-by: default avatarManivannan Sadhasivam <mani@kernel.org>
Signed-off-by: default avatarNiklas Cassel <cassel@kernel.org>
Signed-off-by: default avatarManivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20250625102347.1205584-15-cassel@kernel.org
parent 80dc18a0

drivers/pci/controller/dwc/pcie-designware.c

+3 −3
Original line number Diff line number Diff line
@@ -702,14 +702,14 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) 
	int retries;



	/* Check if the link is up or not */

	for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {

	for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {

		if (dw_pcie_link_up(pci))

			break;



		msleep(LINK_WAIT_SLEEP_MS);

		msleep(PCIE_LINK_WAIT_SLEEP_MS);

	}



	if (retries >= LINK_WAIT_MAX_RETRIES) {

	if (retries >= PCIE_LINK_WAIT_MAX_RETRIES) {

		dev_info(pci->dev, "Phy link never came up\n");

		return -ETIMEDOUT;

	}

drivers/pci/controller/dwc/pcie-designware.h

+0 −4
Original line number Diff line number Diff line
@@ -62,10 +62,6 @@ 
#define dw_pcie_cap_set(_pci, _cap) \

	set_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps)



/* Parameters for the waiting for link up routine */

#define LINK_WAIT_MAX_RETRIES		10

#define LINK_WAIT_SLEEP_MS		90



/* Parameters for the waiting for iATU enabled routine */

#define LINK_WAIT_MAX_IATU_RETRIES	5

#define LINK_WAIT_IATU			9

drivers/pci/pci.h

+4 −0
Original line number Diff line number Diff line
@@ -56,6 +56,10 @@ struct pcie_tlp_log; 
 */

#define PCIE_RESET_CONFIG_WAIT_MS	100



/* Parameters for the waiting for link up routine */

#define PCIE_LINK_WAIT_MAX_RETRIES	10

#define PCIE_LINK_WAIT_SLEEP_MS		90



/* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */

#define PCIE_MSG_TYPE_R_RC	0

#define PCIE_MSG_TYPE_R_ADDR	1