Commit 485380f7 authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amdgpu: Check RRMT status for VCN v4.0.3



RRMT could get dynamically enabled/disabled by PSP firmware. Read the
status from register for reading RRMT status. For VFs, this is not
accessible, hence assume that it's always disabled for now.

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarSathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 822b13d1
Loading
Loading
Loading
Loading
+7 −0
Original line number Diff line number Diff line
@@ -238,6 +238,12 @@

#define AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING 2

enum amdgpu_vcn_caps {
	AMDGPU_VCN_RRMT_ENABLED,
};

#define AMDGPU_VCN_CAPS(caps) BIT(AMDGPU_VCN_##caps)

enum fw_queue_mode {
	FW_QUEUE_RING_RESET = 1,
	FW_QUEUE_DPG_HOLD_OFF = 2,
@@ -345,6 +351,7 @@ struct amdgpu_vcn {
	uint32_t		*ip_dump;

	uint32_t		supported_reset;
	uint32_t		caps;
};

struct amdgpu_fw_shared_rb_ptrs_struct {
+6 −2
Original line number Diff line number Diff line
@@ -98,8 +98,7 @@ static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev,

static inline bool vcn_v4_0_3_normalizn_reqd(struct amdgpu_device *adev)
{
	return (amdgpu_sriov_vf(adev) ||
		(amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)));
	return (adev->vcn.caps & AMDGPU_VCN_CAPS(RRMT_ENABLED)) == 0;
}

/**
@@ -295,6 +294,11 @@ static int vcn_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block)
			ring->sched.ready = true;
		}
	} else {
		/* This flag is not set for VF, assumed to be disabled always */
		if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) &
		    0x100)
			adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED);

		for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
			struct amdgpu_vcn4_fw_shared *fw_shared;