Commit 48795f90 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86_cpu_for_v6.14_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 cpuid updates from Borislav Petkov:

 - Remove the less generic CPU matching infra around struct x86_cpu_desc
   and use the generic struct x86_cpu_id thing

 - Remove magic naked numbers for CPUID functions and use proper defines
   of the prefix CPUID_LEAF_*. Consolidate some of the crazy use around
   the tree

 - Smaller cleanups and improvements

* tag 'x86_cpu_for_v6.14_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/cpu: Make all all CPUID leaf names consistent
  x86/fpu: Remove unnecessary CPUID level check
  x86/fpu: Move CPUID leaf definitions to common code
  x86/tsc: Remove CPUID "frequency" leaf magic numbers.
  x86/tsc: Move away from TSC leaf magic numbers
  x86/cpu: Move TSC CPUID leaf definition
  x86/cpu: Refresh DCA leaf reading code
  x86/cpu: Remove unnecessary MwAIT leaf checks
  x86/cpu: Use MWAIT leaf definition
  x86/cpu: Move MWAIT leaf definition to common header
  x86/cpu: Remove 'x86_cpu_desc' infrastructure
  x86/cpu: Move AMD erratum 1386 table over to 'x86_cpu_id'
  x86/cpu: Replace PEBS use of 'x86_cpu_desc' use with 'x86_cpu_id'
  x86/cpu: Expose only stepping min/max interface
  x86/cpu: Introduce new microcode matching helper
  x86/cpufeature: Document cpu_feature_enabled() as the default to use
  x86/paravirt: Remove the WBINVD callback
  x86/cpufeatures: Free up unused feature bits
parents 13b6931c e5d3a578

arch/x86/events/intel/core.c

+26 −36
Original line number Diff line number Diff line
@@ -5381,42 +5381,32 @@ static __init void intel_clovertown_quirk(void) 
	x86_pmu.pebs_constraints = NULL;

}



static const struct x86_cpu_desc isolation_ucodes[] = {

	INTEL_CPU_DESC(INTEL_HASWELL,		 3, 0x0000001f),

	INTEL_CPU_DESC(INTEL_HASWELL_L,		 1, 0x0000001e),

	INTEL_CPU_DESC(INTEL_HASWELL_G,		 1, 0x00000015),

	INTEL_CPU_DESC(INTEL_HASWELL_X,		 2, 0x00000037),

	INTEL_CPU_DESC(INTEL_HASWELL_X,		 4, 0x0000000a),

	INTEL_CPU_DESC(INTEL_BROADWELL,		 4, 0x00000023),

	INTEL_CPU_DESC(INTEL_BROADWELL_G,	 1, 0x00000014),

	INTEL_CPU_DESC(INTEL_BROADWELL_D,	 2, 0x00000010),

	INTEL_CPU_DESC(INTEL_BROADWELL_D,	 3, 0x07000009),

	INTEL_CPU_DESC(INTEL_BROADWELL_D,	 4, 0x0f000009),

	INTEL_CPU_DESC(INTEL_BROADWELL_D,	 5, 0x0e000002),

	INTEL_CPU_DESC(INTEL_BROADWELL_X,	 1, 0x0b000014),

	INTEL_CPU_DESC(INTEL_SKYLAKE_X,		 3, 0x00000021),

	INTEL_CPU_DESC(INTEL_SKYLAKE_X,		 4, 0x00000000),

	INTEL_CPU_DESC(INTEL_SKYLAKE_X,		 5, 0x00000000),

	INTEL_CPU_DESC(INTEL_SKYLAKE_X,		 6, 0x00000000),

	INTEL_CPU_DESC(INTEL_SKYLAKE_X,		 7, 0x00000000),

	INTEL_CPU_DESC(INTEL_SKYLAKE_X,		11, 0x00000000),

	INTEL_CPU_DESC(INTEL_SKYLAKE_L,		 3, 0x0000007c),

	INTEL_CPU_DESC(INTEL_SKYLAKE,		 3, 0x0000007c),

	INTEL_CPU_DESC(INTEL_KABYLAKE,		 9, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE_L,	 9, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE_L,	10, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE_L,	11, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE_L,	12, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE,		10, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE,		11, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE,		12, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE,		13, 0x0000004e),

static const struct x86_cpu_id isolation_ucodes[] = {

	X86_MATCH_VFM_STEPS(INTEL_HASWELL,	 3,  3, 0x0000001f),

	X86_MATCH_VFM_STEPS(INTEL_HASWELL_L,	 1,  1, 0x0000001e),

	X86_MATCH_VFM_STEPS(INTEL_HASWELL_G,	 1,  1, 0x00000015),

	X86_MATCH_VFM_STEPS(INTEL_HASWELL_X,	 2,  2, 0x00000037),

	X86_MATCH_VFM_STEPS(INTEL_HASWELL_X,	 4,  4, 0x0000000a),

	X86_MATCH_VFM_STEPS(INTEL_BROADWELL,	 4,  4, 0x00000023),

	X86_MATCH_VFM_STEPS(INTEL_BROADWELL_G,	 1,  1, 0x00000014),

	X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D,	 2,  2, 0x00000010),

	X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D,	 3,  3, 0x07000009),

	X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D,	 4,  4, 0x0f000009),

	X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D,	 5,  5, 0x0e000002),

	X86_MATCH_VFM_STEPS(INTEL_BROADWELL_X,	 1,  1, 0x0b000014),

	X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X,	 3,  3, 0x00000021),

	X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X,	 4,  7, 0x00000000),

	X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X,	11, 11, 0x00000000),

	X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_L,	 3,  3, 0x0000007c),

	X86_MATCH_VFM_STEPS(INTEL_SKYLAKE,	 3,  3, 0x0000007c),

	X86_MATCH_VFM_STEPS(INTEL_KABYLAKE,	 9, 13, 0x0000004e),

	X86_MATCH_VFM_STEPS(INTEL_KABYLAKE_L,	 9, 12, 0x0000004e),

	{}

};



static void intel_check_pebs_isolation(void)

{

	x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes);

	x86_pmu.pebs_no_isolation = !x86_match_min_microcode_rev(isolation_ucodes);

}



static __init void intel_pebs_isolation_quirk(void)
@@ -5426,16 +5416,16 @@ static __init void intel_pebs_isolation_quirk(void) 
	intel_check_pebs_isolation();

}



static const struct x86_cpu_desc pebs_ucodes[] = {

	INTEL_CPU_DESC(INTEL_SANDYBRIDGE,	7, 0x00000028),

	INTEL_CPU_DESC(INTEL_SANDYBRIDGE_X,	6, 0x00000618),

	INTEL_CPU_DESC(INTEL_SANDYBRIDGE_X,	7, 0x0000070c),

static const struct x86_cpu_id pebs_ucodes[] = {

	X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE,	7, 7, 0x00000028),

	X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X,	6, 6, 0x00000618),

	X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X,	7, 7, 0x0000070c),

	{}

};



static bool intel_snb_pebs_broken(void)

{

	return !x86_cpu_has_min_microcode_rev(pebs_ucodes);

	return !x86_match_min_microcode_rev(pebs_ucodes);

}



static void intel_snb_check_microcode(void)

arch/x86/events/intel/pt.c

+3 −2
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#include <linux/slab.h>

#include <linux/device.h>



#include <asm/cpuid.h>

#include <asm/perf_event.h>

#include <asm/insn.h>

#include <asm/io.h>
@@ -201,10 +202,10 @@ static int __init pt_pmu_hw_init(void) 
	 * otherwise, zero for numerator stands for "not enumerated"

	 * as per SDM

	 */

	if (boot_cpu_data.cpuid_level >= CPUID_TSC_LEAF) {

	if (boot_cpu_data.cpuid_level >= CPUID_LEAF_TSC) {

		u32 eax, ebx, ecx, edx;



		cpuid(CPUID_TSC_LEAF, &eax, &ebx, &ecx, &edx);

		cpuid(CPUID_LEAF_TSC, &eax, &ebx, &ecx, &edx);



		pt_pmu.tsc_art_num = ebx;

		pt_pmu.tsc_art_den = eax;

arch/x86/events/intel/pt.h

+0 −3
Original line number Diff line number Diff line
@@ -37,9 +37,6 @@ struct topa_entry { 
	u64	rsvd4	: 12;

};



/* TSC to Core Crystal Clock Ratio */

#define CPUID_TSC_LEAF		0x15



struct pt_pmu {

	struct pmu		pmu;

	u32			caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];

arch/x86/include/asm/cpu_device_id.h

+9 −42
Original line number Diff line number Diff line
@@ -56,7 +56,6 @@ 
/* x86_cpu_id::flags */

#define X86_CPU_ID_FLAG_ENTRY_VALID	BIT(0)



#define X86_STEPPINGS(mins, maxs)    GENMASK(maxs, mins)

/**

 * X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE - Base macro for CPU matching

 * @_vendor:	The vendor name, e.g. INTEL, AMD, HYGON, ..., ANY
@@ -208,6 +207,7 @@ 
		VFM_MODEL(vfm),				\

		X86_STEPPING_ANY, X86_FEATURE_ANY, data)



#define __X86_STEPPINGS(mins, maxs)    GENMASK(maxs, mins)

/**

 * X86_MATCH_VFM_STEPPINGS - Match encoded vendor/family/model/stepping

 * @vfm:	Encoded 8-bits each for vendor, family, model
@@ -218,12 +218,13 @@ 
 *

 * feature is set to wildcard

 */

#define X86_MATCH_VFM_STEPPINGS(vfm, steppings, data)	\

#define X86_MATCH_VFM_STEPS(vfm, min_step, max_step, data)	\

	X86_MATCH_VENDORID_FAM_MODEL_STEPPINGS_FEATURE(		\

		VFM_VENDOR(vfm),				\

		VFM_FAMILY(vfm),				\

		VFM_MODEL(vfm),					\

		steppings, X86_FEATURE_ANY, data)

		__X86_STEPPINGS(min_step, max_step),		\

		X86_FEATURE_ANY, data)



/**

 * X86_MATCH_VFM_FEATURE - Match encoded vendor/family/model/feature
@@ -242,41 +243,7 @@ 
		VFM_MODEL(vfm),				\

		X86_STEPPING_ANY, feature, data)



/*

 * Match specific microcode revisions.

 *

 * vendor/family/model/stepping must be all set.

 *

 * Only checks against the boot CPU.  When mixed-stepping configs are

 * valid for a CPU model, add a quirk for every valid stepping and

 * do the fine-tuning in the quirk handler.

 */



struct x86_cpu_desc {

	u8	x86_family;

	u8	x86_vendor;

	u8	x86_model;

	u8	x86_stepping;

	u32	x86_microcode_rev;

};



#define INTEL_CPU_DESC(vfm, stepping, revision) {		\

	.x86_family		= VFM_FAMILY(vfm),		\

	.x86_vendor		= VFM_VENDOR(vfm),		\

	.x86_model		= VFM_MODEL(vfm),		\

	.x86_stepping		= (stepping),			\

	.x86_microcode_rev	= (revision),			\

}



#define AMD_CPU_DESC(fam, model, stepping, revision) {		\

	.x86_family		= (fam),			\

	.x86_vendor		= X86_VENDOR_AMD,		\

	.x86_model		= (model),			\

	.x86_stepping		= (stepping),			\

	.x86_microcode_rev	= (revision),			\

}



extern const struct x86_cpu_id *x86_match_cpu(const struct x86_cpu_id *match);

extern bool x86_cpu_has_min_microcode_rev(const struct x86_cpu_desc *table);

extern bool x86_match_min_microcode_rev(const struct x86_cpu_id *table);



#endif /* _ASM_X86_CPU_DEVICE_ID */

arch/x86/include/asm/cpufeature.h

+6 −12
Original line number Diff line number Diff line
@@ -132,11 +132,12 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; 
	 x86_this_cpu_test_bit(bit, cpu_info.x86_capability))



/*

 * This macro is for detection of features which need kernel

 * infrastructure to be used.  It may *not* directly test the CPU

 * itself.  Use the cpu_has() family if you want true runtime

 * testing of CPU features, like in hypervisor code where you are

 * supporting a possible guest feature where host support for it

 * This is the default CPU features testing macro to use in code.

 *

 * It is for detection of features which need kernel infrastructure to be

 * used.  It may *not* directly test the CPU itself.  Use the cpu_has() family

 * if you want true runtime testing of CPU features, like in hypervisor code

 * where you are supporting a possible guest feature where host support for it

 * is not relevant.

 */

#define cpu_feature_enabled(bit)	\
@@ -161,13 +162,6 @@ extern void clear_cpu_cap(struct cpuinfo_x86 *c, unsigned int bit); 
#define setup_force_cpu_bug(bit) setup_force_cpu_cap(bit)



/*

 * Static testing of CPU features. Used the same as boot_cpu_has(). It

 * statically patches the target code for additional performance. Use

 * static_cpu_has() only in fast paths, where every cycle counts. Which

 * means that the boot_cpu_has() variant is already fast enough for the

 * majority of cases and you should stick to using it as it is generally

 * only two instructions: a RIP-relative MOV and a TEST.

 *

 * Do not use an "m" constraint for [cap_byte] here: gcc doesn't know

 * that this is only used on a fallback path and will sometimes cause

 * it to manifest the address of boot_cpu_data in a register, fouling