Commit 492689ba authored by Ian Rogers's avatar Ian Rogers Committed by Namhyung Kim
Browse files

perf vendor events intel: Update sierraforest events from 1.12 to 1.13 

The updated events were published in:
https://github.com/intel/perfmon/commit/445e38f5128592f8b5c38da30267fff025e37613



Signed-off-by: default avatarIan Rogers <irogers@google.com>
Reviewed-by: default avatarDapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: default avatarNamhyung Kim <namhyung@kernel.org>
parent 77621ef2

tools/perf/pmu-events/arch/x86/mapfile.csv

+1 −1
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ GenuineIntel-6-CC,v1.02,pantherlake,core 
GenuineIntel-6-A7,v1.04,rocketlake,core

GenuineIntel-6-2A,v19,sandybridge,core

GenuineIntel-6-8F,v1.35,sapphirerapids,core

GenuineIntel-6-AF,v1.12,sierraforest,core

GenuineIntel-6-AF,v1.13,sierraforest,core

GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core

GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v59,skylake,core

GenuineIntel-6-55-[01234],v1.37,skylakex,core

tools/perf/pmu-events/arch/x86/sierraforest/cache.json

+10 −10
Original line number Diff line number Diff line
@@ -327,7 +327,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "Counter": "0,1,2,3,4,5,6,7",

        "Counter": "0,1",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024",
@@ -338,7 +338,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "Counter": "0,1,2,3,4,5,6,7",

        "Counter": "0,1",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
@@ -349,7 +349,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "Counter": "0,1,2,3,4,5,6,7",

        "Counter": "0,1",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
@@ -360,7 +360,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "Counter": "0,1,2,3,4,5,6,7",

        "Counter": "0,1",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048",
@@ -371,7 +371,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "Counter": "0,1,2,3,4,5,6,7",

        "Counter": "0,1",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
@@ -382,7 +382,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "Counter": "0,1,2,3,4,5,6,7",

        "Counter": "0,1",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
@@ -393,7 +393,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "Counter": "0,1,2,3,4,5,6,7",

        "Counter": "0,1",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
@@ -404,7 +404,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "Counter": "0,1,2,3,4,5,6,7",

        "Counter": "0,1",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
@@ -415,7 +415,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "Counter": "0,1,2,3,4,5,6,7",

        "Counter": "0,1",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
@@ -426,7 +426,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "Counter": "0,1,2,3,4,5,6,7",

        "Counter": "0,1",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",

tools/perf/pmu-events/arch/x86/sierraforest/uncore-cache.json

+9 −0
Original line number Diff line number Diff line
@@ -9,6 +9,15 @@ 
        "PublicDescription": "UNC_CHACMS_CLOCKTICKS",

        "Unit": "CHACMS"

    },

    {

        "BriefDescription": "UNC_CHACMS_DISTRESS_ASSERTED",

        "Counter": "0,1,2,3",

        "EventCode": "0x35",

        "EventName": "UNC_CHACMS_DISTRESS_ASSERTED",

        "PerPkg": "1",

        "PortMask": "0x000",

        "Unit": "CHACMS"

    },

    {

        "BriefDescription": "Counts the number of cycles FAST trigger is received from the global FAST distress wire.",

        "Counter": "0,1,2,3",