Commit 49862587 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-fixes-2025-08-26' of https://gitlab.freedesktop.org/drm/msm into drm-fixes 



Fixes for v6.17-rc4

Core/GPU:
- fix comment doc warning in gpuvm
- fix build with KMS disabled
- fix pgtable setup/teardown race
- global fault counter fix
- various error path fixes
- GPU devcoredump snapshot fixes
- handle in-place VM_BIND remaps to solve turnip vm update race
- skip re-emitting IBs for unusable VMs
- Don't use %pK through printk
- moved display snapshot init earlier, fixing a crash

DPU:
- Fixed crash in virtual plane checking code
- Fixed mode comparison in virtual plane checking code

DSI:
- Adjusted width of resulution-related registers
- Fixed locking issue on 14nm PLLs

UBWC (per Bjorn's ack)
- Added UBWC configuration for several missing platforms (fixing
  regression)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <rob.clark@oss.qualcomm.com>
Link: https://lore.kernel.org/r/CACSVV02+u1VW1dzuz6JWwVEfpgTj6Y-JXMH+vX43KsKTVsW+Yg@mail.gmail.com
parents 4b1c24ef 3cf6147f

Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml

+0 −1
Original line number Diff line number Diff line
@@ -60,7 +60,6 @@ properties: 
          - const: bus

          - const: core

          - const: vsync

          - const: lut

          - const: tbu

          - const: tbu_rt

        # MSM8996 has additional iommu clock

drivers/gpu/drm/drm_gpuvm.c

+1 −1
Original line number Diff line number Diff line
@@ -2430,7 +2430,7 @@ static const struct drm_gpuvm_ops lock_ops = { 
 * remapped, and locks+prepares (drm_exec_prepare_object()) objects that

 * will be newly mapped.

 *

 * The expected usage is:

 * The expected usage is::

 *

 * .. code-block:: c

 *

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

+33 −14
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ 
static const unsigned int *gen7_0_0_external_core_regs[] __always_unused;

static const unsigned int *gen7_2_0_external_core_regs[] __always_unused;

static const unsigned int *gen7_9_0_external_core_regs[] __always_unused;

static struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] __always_unused;

static const struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] __always_unused;

static const u32 gen7_9_0_cx_debugbus_blocks[] __always_unused;



#include "adreno_gen7_0_0_snapshot.h"
@@ -174,8 +174,15 @@ static int a6xx_crashdumper_run(struct msm_gpu *gpu, 
static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset,

		u32 *data)

{

	u32 reg = A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(offset) |

	u32 reg;



	if (to_adreno_gpu(gpu)->info->family >= ADRENO_7XX_GEN1) {

		reg = A7XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(offset) |

			A7XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(block);

	} else {

		reg = A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(offset) |

			A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(block);

	}



	gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_A, reg);

	gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_B, reg);
@@ -198,11 +205,18 @@ static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset, 
	readl((ptr) + ((offset) << 2))



/* read a value from the CX debug bus */

static int cx_debugbus_read(void __iomem *cxdbg, u32 block, u32 offset,

static int cx_debugbus_read(struct msm_gpu *gpu, void __iomem *cxdbg, u32 block, u32 offset,

		u32 *data)

{

	u32 reg = A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(offset) |

	u32 reg;



	if (to_adreno_gpu(gpu)->info->family >= ADRENO_7XX_GEN1) {

		reg = A7XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(offset) |

			A7XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(block);

	} else {

		reg = A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(offset) |

			A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(block);

	}



	cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A, reg);

	cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B, reg);
@@ -315,7 +329,8 @@ static void a6xx_get_debugbus_block(struct msm_gpu *gpu, 
		ptr += debugbus_read(gpu, block->id, i, ptr);

}



static void a6xx_get_cx_debugbus_block(void __iomem *cxdbg,

static void a6xx_get_cx_debugbus_block(struct msm_gpu *gpu,

		void __iomem *cxdbg,

		struct a6xx_gpu_state *a6xx_state,

		const struct a6xx_debugbus_block *block,

		struct a6xx_gpu_state_obj *obj)
@@ -330,7 +345,7 @@ static void a6xx_get_cx_debugbus_block(void __iomem *cxdbg, 
	obj->handle = block;



	for (ptr = obj->data, i = 0; i < block->count; i++)

		ptr += cx_debugbus_read(cxdbg, block->id, i, ptr);

		ptr += cx_debugbus_read(gpu, cxdbg, block->id, i, ptr);

}



static void a6xx_get_debugbus_blocks(struct msm_gpu *gpu,
@@ -423,8 +438,9 @@ static void a7xx_get_debugbus_blocks(struct msm_gpu *gpu, 
				a6xx_state, &a7xx_debugbus_blocks[gbif_debugbus_blocks[i]],

				&a6xx_state->debugbus[i + debugbus_blocks_count]);

		}

	}



		a6xx_state->nr_debugbus = total_debugbus_blocks;

	}

}



static void a6xx_get_debugbus(struct msm_gpu *gpu,
@@ -526,7 +542,8 @@ static void a6xx_get_debugbus(struct msm_gpu *gpu, 
			int i;



			for (i = 0; i < nr_cx_debugbus_blocks; i++)

				a6xx_get_cx_debugbus_block(cxdbg,

				a6xx_get_cx_debugbus_block(gpu,

					cxdbg,

					a6xx_state,

					&cx_debugbus_blocks[i],

					&a6xx_state->cx_debugbus[i]);
@@ -759,15 +776,15 @@ static void a7xx_get_cluster(struct msm_gpu *gpu, 
	size_t datasize;

	int i, regcount = 0;



	/* Some clusters need a selector register to be programmed too */

	if (cluster->sel)

		in += CRASHDUMP_WRITE(in, cluster->sel->cd_reg, cluster->sel->val);



	in += CRASHDUMP_WRITE(in, REG_A7XX_CP_APERTURE_CNTL_CD,

		A7XX_CP_APERTURE_CNTL_CD_PIPE(cluster->pipe_id) |

		A7XX_CP_APERTURE_CNTL_CD_CLUSTER(cluster->cluster_id) |

		A7XX_CP_APERTURE_CNTL_CD_CONTEXT(cluster->context_id));



	/* Some clusters need a selector register to be programmed too */

	if (cluster->sel)

		in += CRASHDUMP_WRITE(in, cluster->sel->cd_reg, cluster->sel->val);



	for (i = 0; cluster->regs[i] != UINT_MAX; i += 2) {

		int count = RANGE(cluster->regs, i);
@@ -1796,6 +1813,7 @@ static void a7xx_show_shader(struct a6xx_gpu_state_obj *obj, 


	print_name(p, "  - type: ", a7xx_statetype_names[block->statetype]);

	print_name(p, "    - pipe: ", a7xx_pipe_names[block->pipeid]);

	drm_printf(p, "    - location: %d\n", block->location);



	for (i = 0; i < block->num_sps; i++) {

		drm_printf(p, "      - sp: %d\n", i);
@@ -1873,6 +1891,7 @@ static void a7xx_show_dbgahb_cluster(struct a6xx_gpu_state_obj *obj, 
		print_name(p, "  - pipe: ", a7xx_pipe_names[dbgahb->pipe_id]);

		print_name(p, "    - cluster-name: ", a7xx_cluster_names[dbgahb->cluster_id]);

		drm_printf(p, "      - context: %d\n", dbgahb->context_id);

		drm_printf(p, "      - location: %d\n", dbgahb->location_id);

		a7xx_show_registers_indented(dbgahb->regs, obj->data, p, 4);

	}

}

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h

+19 −19
Original line number Diff line number Diff line
@@ -419,47 +419,47 @@ static const struct a6xx_indexed_registers a6xx_indexed_reglist[] = { 
		REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },

	{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,

		REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL },

	{ "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,

	{ "CP_SQE_UCODE_DBG", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,

		REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL },

	{ "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR,

	{ "CP_ROQ_DBG", REG_A6XX_CP_ROQ_DBG_ADDR,

		REG_A6XX_CP_ROQ_DBG_DATA, 0, a6xx_get_cp_roq_size},

};



static const struct a6xx_indexed_registers a7xx_indexed_reglist[] = {

	{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,

		REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },

		REG_A6XX_CP_SQE_STAT_DATA, 0x40, NULL },

	{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,

		REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL },

	{ "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,

	{ "CP_SQE_UCODE_DBG", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,

		REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL },

	{ "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_SQE_STAT_ADDR,

		REG_A7XX_CP_BV_SQE_STAT_DATA, 0x33, NULL },

	{ "CP_BV_DRAW_STATE_ADDR", REG_A7XX_CP_BV_DRAW_STATE_ADDR,

	{ "CP_BV_SQE_STAT", REG_A7XX_CP_BV_SQE_STAT_ADDR,

		REG_A7XX_CP_BV_SQE_STAT_DATA, 0x40, NULL },

	{ "CP_BV_DRAW_STATE", REG_A7XX_CP_BV_DRAW_STATE_ADDR,

		REG_A7XX_CP_BV_DRAW_STATE_DATA, 0x100, NULL },

	{ "CP_BV_SQE_UCODE_DBG_ADDR", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR,

	{ "CP_BV_SQE_UCODE_DBG", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR,

		REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA, 0x8000, NULL },

	{ "CP_SQE_AC_STAT_ADDR", REG_A7XX_CP_SQE_AC_STAT_ADDR,

		REG_A7XX_CP_SQE_AC_STAT_DATA, 0x33, NULL },

	{ "CP_LPAC_DRAW_STATE_ADDR", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR,

	{ "CP_SQE_AC_STAT", REG_A7XX_CP_SQE_AC_STAT_ADDR,

		REG_A7XX_CP_SQE_AC_STAT_DATA, 0x40, NULL },

	{ "CP_LPAC_DRAW_STATE", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR,

		REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x100, NULL },

	{ "CP_SQE_AC_UCODE_DBG_ADDR", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR,

	{ "CP_SQE_AC_UCODE_DBG", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR,

		REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA, 0x8000, NULL },

	{ "CP_LPAC_FIFO_DBG_ADDR", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR,

	{ "CP_LPAC_FIFO_DBG", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR,

		REG_A7XX_CP_LPAC_FIFO_DBG_DATA, 0x40, NULL },

	{ "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR,

	{ "CP_ROQ_DBG", REG_A6XX_CP_ROQ_DBG_ADDR,

		REG_A6XX_CP_ROQ_DBG_DATA, 0, a7xx_get_cp_roq_size },

};



static const struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {

	"CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,

	"CP_MEM_POOL_DBG", REG_A6XX_CP_MEM_POOL_DBG_ADDR,

		REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060, NULL,

};



static const struct a6xx_indexed_registers a7xx_cp_bv_mempool_indexed[] = {

	{ "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,

		REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2100, NULL },

	{ "CP_BV_MEMPOOL", REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR,

		REG_A7XX_CP_BV_MEM_POOL_DBG_DATA, 0x2100, NULL },

	{ "CP_MEM_POOL_DBG", REG_A6XX_CP_MEM_POOL_DBG_ADDR,

		REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2200, NULL },

	{ "CP_BV_MEM_POOL_DBG", REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR,

		REG_A7XX_CP_BV_MEM_POOL_DBG_DATA, 0x2200, NULL },

};



#define DEBUGBUS(_id, _count) { .id = _id, .name = #_id, .count = _count }

drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h

+13 −6
Original line number Diff line number Diff line
@@ -81,7 +81,7 @@ static const u32 gen7_0_0_debugbus_blocks[] = { 
	A7XX_DBGBUS_USPTP_7,

};



static struct gen7_shader_block gen7_0_0_shader_blocks[] = {

static const struct gen7_shader_block gen7_0_0_shader_blocks[] = {

	{A7XX_TP0_TMO_DATA,                 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},

	{A7XX_TP0_SMO_DATA,                  0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},

	{A7XX_TP0_MIPMAP_BASE_DATA,         0x3c0, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
@@ -668,12 +668,19 @@ static const u32 gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers[] = { 
};

static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers), 8));



/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_BR */

static const u32 gen7_0_0_tpl1_noncontext_pipe_br_registers[] = {

/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_NONE */

static const u32 gen7_0_0_tpl1_noncontext_pipe_none_registers[] = {

	0x0b600, 0x0b600, 0x0b602, 0x0b602, 0x0b604, 0x0b604, 0x0b608, 0x0b60c,

	0x0b60f, 0x0b621, 0x0b630, 0x0b633,

	UINT_MAX, UINT_MAX,

};

static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_none_registers), 8));



/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_BR */

static const u32 gen7_0_0_tpl1_noncontext_pipe_br_registers[] = {

	 0x0b600, 0x0b600,

	 UINT_MAX, UINT_MAX,

};

static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_br_registers), 8));



/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_LPAC */
@@ -695,7 +702,7 @@ static const struct gen7_sel_reg gen7_0_0_rb_rbp_sel = { 
	.val = 0x9,

};



static struct gen7_cluster_registers gen7_0_0_clusters[] = {

static const struct gen7_cluster_registers gen7_0_0_clusters[] = {

	{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,

		gen7_0_0_noncontext_pipe_br_registers, },

	{ A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT,
@@ -764,7 +771,7 @@ static struct gen7_cluster_registers gen7_0_0_clusters[] = { 
		gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, },

};



static struct gen7_sptp_cluster_registers gen7_0_0_sptp_clusters[] = {

static const struct gen7_sptp_cluster_registers gen7_0_0_sptp_clusters[] = {

	{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,

		gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 },

	{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
@@ -914,7 +921,7 @@ static const u32 gen7_0_0_dpm_registers[] = { 
};

static_assert(IS_ALIGNED(sizeof(gen7_0_0_dpm_registers), 8));



static struct gen7_reg_list gen7_0_0_reg_list[] = {

static const struct gen7_reg_list gen7_0_0_reg_list[] = {

	{ gen7_0_0_gpu_registers, NULL },

	{ gen7_0_0_cx_misc_registers, NULL },

	{ gen7_0_0_dpm_registers, NULL },