Unverified Commit 4cbc0864 authored by Vinay Belgaumkar's avatar Vinay Belgaumkar Committed by Rodrigo Vivi
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drm/xe: Enable media sampler power gating 



Where applicable, enable media sampler power gating. Also, add
it to the powergate_info debugfs.

v2: Remove the sampler powergate status since it is cleared quickly anyway.
v3: Use vcs mask (Rodrigo) and fix the version check for media
v4: Remove extra spaces
v5: Media samplers are independent of vcs mask,
    use Media version 1255 (Matt Roper)

Fixes: 38e8c418 ("drm/xe: Enable Coarse Power Gating")
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarVinay Belgaumkar <vinay.belgaumkar@intel.com>
Link: https://lore.kernel.org/r/20251010011047.2047584-1-vinay.belgaumkar@intel.com


Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 75188605

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -342,6 +342,7 @@ 
#define POWERGATE_ENABLE			XE_REG(0xa210)

#define   RENDER_POWERGATE_ENABLE		REG_BIT(0)

#define   MEDIA_POWERGATE_ENABLE		REG_BIT(1)

#define   MEDIA_SAMPLERS_POWERGATE_ENABLE	REG_BIT(2)

#define   VDN_HCP_POWERGATE_ENABLE(n)		REG_BIT(3 + 2 * (n))

#define   VDN_MFXVDENC_POWERGATE_ENABLE(n)	REG_BIT(4 + 2 * (n))

drivers/gpu/drm/xe/xe_gt_idle.c

+8 −0
Original line number Diff line number Diff line
@@ -124,6 +124,9 @@ void xe_gt_idle_enable_pg(struct xe_gt *gt) 
	if (xe_gt_is_main_type(gt))

		gtidle->powergate_enable |= RENDER_POWERGATE_ENABLE;



	if (MEDIA_VERx100(xe) >= 1100 && MEDIA_VERx100(xe) < 1255)

		gtidle->powergate_enable |= MEDIA_SAMPLERS_POWERGATE_ENABLE;



	if (xe->info.platform != XE_DG1) {

		for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) {

			if ((gt->info.engine_mask & BIT(i)))
@@ -246,6 +249,11 @@ int xe_gt_idle_pg_print(struct xe_gt *gt, struct drm_printer *p) 
				drm_printf(p, "Media Slice%d Power Gate Status: %s\n", n,

					   str_up_down(pg_status & media_slices[n].status_bit));

	}



	if (MEDIA_VERx100(xe) >= 1100 && MEDIA_VERx100(xe) < 1255)

		drm_printf(p, "Media Samplers Power Gating Enabled: %s\n",

			   str_yes_no(pg_enabled & MEDIA_SAMPLERS_POWERGATE_ENABLE));



	return 0;

}