Commit 4d911c7a authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvm-riscv-6.13-2' of https://github.com/kvm-riscv/linux into HEAD 

KVM/riscv changes for 6.13 part #2

- Svade and Svadu extension support for Host and Guest/VM
parents c1668520 c74bfe4f

Documentation/devicetree/bindings/riscv/extensions.yaml

+28 −0
Original line number Diff line number Diff line
@@ -171,6 +171,34 @@ properties: 
            ratified at commit 3f9ed34 ("Add ability to manually trigger

            workflow. (#2)") of riscv-time-compare.



        - const: svade

          description: |

            The standard Svade supervisor-level extension for SW-managed PTE A/D

            bit updates as ratified in the 20240213 version of the privileged

            ISA specification.



            Both Svade and Svadu extensions control the hardware behavior when

            the PTE A/D bits need to be set. The default behavior for the four

            possible combinations of these extensions in the device tree are:

            1) Neither Svade nor Svadu present in DT => It is technically

               unknown whether the platform uses Svade or Svadu. Supervisor

               software should be prepared to handle either hardware updating

               of the PTE A/D bits or page faults when they need updated.

            2) Only Svade present in DT => Supervisor must assume Svade to be

               always enabled.

            3) Only Svadu present in DT => Supervisor must assume Svadu to be

               always enabled.

            4) Both Svade and Svadu present in DT => Supervisor must assume

               Svadu turned-off at boot time. To use Svadu, supervisor must

               explicitly enable it using the SBI FWFT extension.



        - const: svadu

          description: |

            The standard Svadu supervisor-level extension for hardware updating

            of PTE A/D bits as ratified in the 20240528 version of the

            privileged ISA specification. Please refer to Svade dt-binding

            description for more details.



        - const: svinval

          description:

            The standard Svinval supervisor-level extension for fine-grained

arch/riscv/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ config RISCV 
	select ARCH_HAS_FORTIFY_SOURCE

	select ARCH_HAS_GCOV_PROFILE_ALL

	select ARCH_HAS_GIGANTIC_PAGE

	select ARCH_HAS_HW_PTE_YOUNG

	select ARCH_HAS_KCOV

	select ARCH_HAS_KERNEL_FPU_SUPPORT if 64BIT && FPU

	select ARCH_HAS_MEMBARRIER_CALLBACKS

arch/riscv/include/asm/csr.h

+1 −0
Original line number Diff line number Diff line
@@ -199,6 +199,7 @@ 
/* xENVCFG flags */

#define ENVCFG_STCE			(_AC(1, ULL) << 63)

#define ENVCFG_PBMTE			(_AC(1, ULL) << 62)

#define ENVCFG_ADUE			(_AC(1, ULL) << 61)

#define ENVCFG_PMM			(_AC(0x3, ULL) << 32)

#define ENVCFG_PMM_PMLEN_0		(_AC(0x0, ULL) << 32)

#define ENVCFG_PMM_PMLEN_7		(_AC(0x2, ULL) << 32)

arch/riscv/include/asm/hwcap.h

+2 −0
Original line number Diff line number Diff line
@@ -98,6 +98,8 @@ 
#define RISCV_ISA_EXT_SSNPM		89

#define RISCV_ISA_EXT_ZABHA		90

#define RISCV_ISA_EXT_ZICCRSE		91

#define RISCV_ISA_EXT_SVADE		92

#define RISCV_ISA_EXT_SVADU		93



#define RISCV_ISA_EXT_XLINUXENVCFG	127

arch/riscv/include/asm/pgtable.h

+12 −1
Original line number Diff line number Diff line
@@ -113,6 +113,7 @@ 
#include <asm/tlbflush.h>

#include <linux/mm_types.h>

#include <asm/compat.h>

#include <asm/cpufeature.h>



#define __page_val_to_pfn(_val)  (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT)
@@ -284,7 +285,6 @@ static inline pte_t pud_pte(pud_t pud) 
}



#ifdef CONFIG_RISCV_ISA_SVNAPOT

#include <asm/cpufeature.h>



static __always_inline bool has_svnapot(void)

{
@@ -655,6 +655,17 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot) 
	return __pgprot(prot);

}



/*

 * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By

 * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in

 * DT.

 */

#define arch_has_hw_pte_young arch_has_hw_pte_young

static inline bool arch_has_hw_pte_young(void)

{

	return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU);

}



/*

 * THP functions

 */