Commit 4e52054f authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'samsung-clk-6.12' of... 

Merge tag 'samsung-clk-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung

Pull Samsung clk driver updates from Krzysztof Kozlowski:

 - Exynos850: Add clock for Thermal Management Unit
 - Exynos7885: Fix duplicated ID in the header, add missing TOP PLLs and
   add clocks for USB block in the FSYS clock controller
 - ExynosAutov9: Add DPUM clock controller
 - ExynosAutov920: Add new (first) clock controllers: TOP and PERIC0
   (and a bit more complete bindings)

* tag 'samsung-clk-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  clk: samsung: add top clock support for ExynosAuto v920 SoC
  clk: samsung: clk-pll: Add support for pll_531x
  dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings
  clk: samsung: exynos7885: Add USB related clocks to CMU_FSYS
  clk: samsung: clk-pll: Add support for pll_1418x
  clk: samsung: exynosautov9: add dpum clock support
  dt-bindings: clock: exynosautov9: add dpum clock
  clk: samsung: exynos7885: Add missing MUX clocks from PLLs in CMU_TOP
  clk: samsung: exynos7885: Update CLKS_NR_FSYS after bindings fix
  dt-bindings: clock: exynos7885: Add indices for USB clocks
  dt-bindings: clock: exynos7885: Add CMU_TOP PLL MUX indices
  dt-bindings: clock: exynos7885: Fix duplicated binding
  clk: samsung: exynos850: Add TMU clock
  dt-bindings: clock: exynos850: Add TMU clock
parents 8400291e 485e13fe

Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml

+19 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ properties: 
      - samsung,exynosautov9-cmu-top

      - samsung,exynosautov9-cmu-busmc

      - samsung,exynosautov9-cmu-core

      - samsung,exynosautov9-cmu-dpum

      - samsung,exynosautov9-cmu-fsys0

      - samsung,exynosautov9-cmu-fsys1

      - samsung,exynosautov9-cmu-fsys2
@@ -109,6 +110,24 @@ allOf: 
            - const: oscclk

            - const: dout_clkcmu_core_bus



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynosautov9-cmu-dpum



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: DPU Main bus clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: bus



  - if:

      properties:

        compatible:

Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml

0 → 100644
+162 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/samsung,exynosautov920-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Samsung ExynosAuto v920 SoC clock controller



maintainers:

  - Sunyeal Hong <sunyeal.hong@samsung.com>

  - Chanwoo Choi <cw00.choi@samsung.com>

  - Krzysztof Kozlowski <krzk@kernel.org>

  - Sylwester Nawrocki <s.nawrocki@samsung.com>



description: |

  ExynosAuto v920 clock controller is comprised of several CMU units, generating

  clocks for different domains. Those CMU units are modeled as separate device

  tree nodes, and might depend on each other. Root clocks in that clock tree are

  two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz).

  The external OSCCLK must be defined as fixed-rate clock in dts.



  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and

  dividers; all other clocks of function blocks (other CMUs) are usually

  derived from CMU_TOP.



  Each clock is assigned an identifier and client nodes can use this identifier

  to specify the clock which they consume. All clocks available for usage

  in clock consumer nodes are defined as preprocessor macros in

  'include/dt-bindings/clock/samsung,exynosautov920.h' header.



properties:

  compatible:

    enum:

      - samsung,exynosautov920-cmu-top

      - samsung,exynosautov920-cmu-peric0

      - samsung,exynosautov920-cmu-peric1

      - samsung,exynosautov920-cmu-misc

      - samsung,exynosautov920-cmu-hsi0

      - samsung,exynosautov920-cmu-hsi1



  clocks:

    minItems: 1

    maxItems: 4



  clock-names:

    minItems: 1

    maxItems: 4



  "#clock-cells":

    const: 1



  reg:

    maxItems: 1



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynosautov920-cmu-top



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (38.4 MHz)



        clock-names:

          items:

            - const: oscclk



  - if:

      properties:

        compatible:

          contains:

            enum:

              - samsung,exynosautov920-cmu-peric0

              - samsung,exynosautov920-cmu-peric1



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (38.4 MHz)

            - description: CMU_PERICn NOC clock (from CMU_TOP)

            - description: CMU_PERICn IP clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: noc

            - const: ip



  - if:

      properties:

        compatible:

          enum:

            - samsung,exynosautov920-cmu-misc

            - samsung,exynosautov920-cmu-hsi0



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (38.4 MHz)

            - description: CMU_MISC/CMU_HSI0 NOC clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: noc



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynosautov920-cmu-hsi1



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (38.4 MHz)

            - description: CMU_HSI1 NOC clock (from CMU_TOP)

            - description: CMU_HSI1 USBDRD clock (from CMU_TOP)

            - description: CMU_HSI1 MMC_CARD clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: noc

            - const: usbdrd

            - const: mmc_card



required:

  - compatible

  - "#clock-cells"

  - clocks

  - clock-names

  - reg



additionalProperties: false



examples:

  # Clock controller node for CMU_PERIC0

  - |

    #include <dt-bindings/clock/samsung,exynosautov920.h>



    cmu_peric0: clock-controller@10800000 {

        compatible = "samsung,exynosautov920-cmu-peric0";

        reg = <0x10800000 0x8000>;

        #clock-cells = <1>;



        clocks = <&xtcxo>,

                 <&cmu_top DOUT_CLKCMU_PERIC0_NOC>,

                 <&cmu_top DOUT_CLKCMU_PERIC0_IP>;

        clock-names = "oscclk",

                      "noc",

                      "ip";

    };



...

drivers/clk/samsung/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o 
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos7885.o

obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos850.o

obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynosautov9.o

obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynosautov920.o

obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-gs101.o

obj-$(CONFIG_S3C64XX_COMMON_CLK)	+= clk-s3c64xx.o

obj-$(CONFIG_S5PV210_COMMON_CLK)	+= clk-s5pv210.o clk-s5pv210-audss.o

drivers/clk/samsung/clk-exynos7885.c

+73 −20
Original line number Diff line number Diff line
@@ -17,10 +17,10 @@ 
#include "clk-exynos-arm64.h"



/* NOTE: Must be equal to the last clock ID increased by one */

#define CLKS_NR_TOP			(CLK_GOUT_FSYS_USB30DRD + 1)

#define CLKS_NR_TOP			(CLK_MOUT_SHARED1_PLL + 1)

#define CLKS_NR_CORE			(CLK_GOUT_TREX_P_CORE_PCLK_P_CORE + 1)

#define CLKS_NR_PERI			(CLK_GOUT_WDT1_PCLK + 1)

#define CLKS_NR_FSYS			(CLK_GOUT_MMC_SDIO_SDCLKIN + 1)

#define CLKS_NR_FSYS			(CLK_FSYS_USB30DRD_REF_CLK + 1)



/* ---- CMU_TOP ------------------------------------------------------------- */
@@ -162,6 +162,10 @@ static const struct samsung_pll_clock top_pll_clks[] __initconst = { 
	    NULL),

};



/* List of parent clocks for Muxes in CMU_TOP */

PNAME(mout_shared0_pll_p)	= { "oscclk", "fout_shared0_pll" };

PNAME(mout_shared1_pll_p)	= { "oscclk", "fout_shared1_pll" };



/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */

PNAME(mout_core_bus_p)		= { "dout_shared0_div2", "dout_shared1_div2",

				    "dout_shared0_div3", "dout_shared0_div3" };
@@ -189,6 +193,12 @@ PNAME(mout_fsys_mmc_sdio_p) = { "dout_shared0_div2", "dout_shared1_div2" }; 
PNAME(mout_fsys_usb30drd_p)	= { "dout_shared0_div4", "dout_shared1_div4" };



static const struct samsung_mux_clock top_mux_clks[] __initconst = {

	/* TOP */

	MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,

	    PLL_CON0_PLL_SHARED0, 4, 1),

	MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,

	    PLL_CON0_PLL_SHARED1, 4, 1),



	/* CORE */

	MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,

	    CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
@@ -232,17 +242,17 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = { 


static const struct samsung_div_clock top_div_clks[] __initconst = {

	/* TOP */

	DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "fout_shared0_pll",

	DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",

	    CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),

	DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll",

	DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",

	    CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),

	DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",

	    CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),

	DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll",

	DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "mout_shared0_pll",

	    CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),

	DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "fout_shared1_pll",

	DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",

	    CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),

	DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll",

	DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",

	    CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),

	DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",

	    CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
@@ -676,30 +686,56 @@ static const struct samsung_cmu_info core_cmu_info __initconst = { 
/* ---- CMU_FSYS ------------------------------------------------------------ */



/* Register Offset definitions for CMU_FSYS (0x13400000) */

#define PLL_LOCKTIME_PLL_USB				0x0000

#define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER		0x0100

#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER		0x0120

#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER		0x0140

#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER		0x0160

#define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER		0x0180

#define PLL_CON0_PLL_USB				0x01a0

#define CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE		0x200c

#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK		0x2030

#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN		0x2034

#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK		0x2038

#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN		0x203c

#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK		0x2040

#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN		0x2044

#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL	0x2068

#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0	0x206c

#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1	0x2070

#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY	0x2074

#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK		0x2078



static const unsigned long fsys_clk_regs[] __initconst = {

	PLL_LOCKTIME_PLL_USB,

	PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER,

	PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER,

	PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER,

	PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,

	PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,

	PLL_CON0_PLL_USB,

	CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE,

	CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK,

	CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN,

	CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK,

	CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN,

	CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK,

	CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,

	CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL,

	CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0,

	CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1,

	CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY,

	CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK,

};



static const struct samsung_pll_rate_table pll_usb_rate_table[] __initconst = {

	PLL_35XX_RATE(26 * MHZ, 50000000U, 400, 13, 4),

};



static const struct samsung_pll_clock fsys_pll_clks[] __initconst = {

	PLL(pll_1418x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk",

	    PLL_LOCKTIME_PLL_USB, PLL_CON0_PLL_USB,

	    pll_usb_rate_table),

};



/* List of parent clocks for Muxes in CMU_FSYS */
@@ -708,6 +744,7 @@ PNAME(mout_fsys_mmc_card_user_p) = { "oscclk", "dout_fsys_mmc_card" }; 
PNAME(mout_fsys_mmc_embd_user_p)	= { "oscclk", "dout_fsys_mmc_embd" };

PNAME(mout_fsys_mmc_sdio_user_p)	= { "oscclk", "dout_fsys_mmc_sdio" };

PNAME(mout_fsys_usb30drd_user_p)	= { "oscclk", "dout_fsys_usb30drd" };

PNAME(mout_usb_pll_p)			= { "oscclk", "fout_usb_pll" };



static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {

	MUX(CLK_MOUT_FSYS_BUS_USER, "mout_fsys_bus_user", mout_fsys_bus_user_p,
@@ -721,12 +758,16 @@ static const struct samsung_mux_clock fsys_mux_clks[] __initconst = { 
	MUX_F(CLK_MOUT_FSYS_MMC_SDIO_USER, "mout_fsys_mmc_sdio_user",

	      mout_fsys_mmc_sdio_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,

	      4, 1, CLK_SET_RATE_PARENT, 0),

	MUX_F(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user",

	MUX(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user",

	      mout_fsys_usb30drd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,

	      4, 1, CLK_SET_RATE_PARENT, 0),

	      4, 1),

	nMUX_F(CLK_MOUT_USB_PLL, "mout_usb_pll", mout_usb_pll_p,

	    PLL_CON0_PLL_USB, 4, 1, CLK_SET_RATE_PARENT, 0),

};



static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {

	GATE(CLK_FSYS_USB20PHY_CLKCORE, "clk_fsys_usb20phy_clkcore", "mout_usb_pll",

	     CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE, 21, CLK_SET_RATE_PARENT, 0),

	GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_fsys_bus_user",

	     CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, 21, 0, 0),

	GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
@@ -742,9 +783,21 @@ static const struct samsung_gate_clock fsys_gate_clks[] __initconst = { 
	GATE(CLK_GOUT_MMC_SDIO_SDCLKIN, "gout_mmc_sdio_sdclkin",

	     "mout_fsys_mmc_sdio_user", CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,

	     21, CLK_SET_RATE_PARENT, 0),

	GATE(CLK_FSYS_USB30DRD_ACLK_20PHYCTRL, "clk_fsys_usb30drd_aclk_20phyctrl",

	     "mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL, 21, 0, 0),

	GATE(CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_0, "clk_fsys_usb30drd_aclk_30phyctrl_0",

	     "mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0, 21, 0, 0),

	GATE(CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_1, "clk_fsys_usb30drd_aclk_30phyctrl_1",

	     "mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1, 21, 0, 0),

	GATE(CLK_FSYS_USB30DRD_BUS_CLK_EARLY, "clk_fsys_usb30drd_bus_clk_early",

	     "mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY, 21, 0, 0),

	GATE(CLK_FSYS_USB30DRD_REF_CLK, "clk_fsys_usb30drd_ref_clk", "mout_fsys_usb30drd_user",

	     CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK, 21, 0, 0),

};



static const struct samsung_cmu_info fsys_cmu_info __initconst = {

	.pll_clks		= fsys_pll_clks,

	.nr_pll_clks		= ARRAY_SIZE(fsys_pll_clks),

	.mux_clks		= fsys_mux_clks,

	.nr_mux_clks		= ARRAY_SIZE(fsys_mux_clks),

	.gate_clks		= fsys_gate_clks,

drivers/clk/samsung/clk-exynos850.c

+6 −1
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ 
#define CLKS_NR_HSI			(CLK_GOUT_HSI_CMU_HSI_PCLK + 1)

#define CLKS_NR_IS			(CLK_GOUT_IS_SYSREG_PCLK + 1)

#define CLKS_NR_MFCMSCL			(CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1)

#define CLKS_NR_PERI			(CLK_GOUT_WDT1_PCLK + 1)

#define CLKS_NR_PERI			(CLK_GOUT_BUSIF_TMU_PCLK + 1)

#define CLKS_NR_CORE			(CLK_GOUT_SPDMA_CORE_ACLK + 1)

#define CLKS_NR_DPU			(CLK_GOUT_DPU_SYSREG_PCLK + 1)
@@ -1921,6 +1921,7 @@ static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = { 
#define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0	0x200c

#define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1	0x2010

#define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2	0x2014

#define CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK	0x2018

#define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK	0x2020

#define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK	0x2024

#define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK	0x2028
@@ -1957,6 +1958,7 @@ static const unsigned long peri_clk_regs[] __initconst = { 
	CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0,

	CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1,

	CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2,

	CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK,

	CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK,

	CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK,

	CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK,
@@ -2068,6 +2070,9 @@ static const struct samsung_gate_clock peri_gate_clks[] __initconst = { 
	GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk",

	     "mout_peri_bus_user",

	     CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(CLK_GOUT_BUSIF_TMU_PCLK, "gout_busif_tmu_pclk",

	     "mout_peri_bus_user",

	     CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK, 21, 0, 0),

};



static const struct samsung_cmu_info peri_cmu_info __initconst = {