Commit 4ee64205 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull clk updates from Stephen Boyd:
 "We've finally gotten rid of the struct clk_ops::round_rate() code
  after months of effort from Brian Masney. Now the only option is to
  use determine_rate(), which is good because that takes a struct
  argument instead of just a couple unsigned longs, allowing us to
  easily modify the way we determine and set rates in the clk tree.

  Beyond that core framework change we've got the typical pile of new
  SoC clk driver additions, fixes for clk data and/or adding missing
  clks because the consumer driver using those clks wasn't ready, etc.
  The usual suspects are all here: Qualcomm, Samsung, Mediatek, and
  Rockchip along with some newcomers making RISC-V SoCs like ESWIN's
  eic700 and Tenstorrent's Atlantis. The clk driver side of this looks
  pretty normal.

  Core:
   - Remove the round_rate() clk op (yay!)

  New Drivers:
   - ESWIN eic700 SoC clk support
   - Econet EN751221 SoC clock/reset support
   - Global TCSR, RPMh, and display clock controller support for the
     Qualcomm Eliza platform
   - TCSR, the multiple global, and the RPMh clock controller support
     for the Qualcomm Nord platform
   - GPU clock controller support for Qualcomm SM8750
   - Video and GPU clock controller support for Qualcomm Glymur
   - Global clock controller support for Qualcomm IPQ5210
   - Axis ARTPEC-9: Add new PLL clocks and new drivers for eight clock
     controllers on the SoC
   - ExynosAutov920: Add G3D (GPU) clock controller
   - Clock driver for the Rockchip RV1103B SoC
   - Initial support for the Renesas RZ/G3L (R9A08G046) SoC
   - Clock and reset controllers (e.g. PRCM) in the Tenstorrent Atlantis SoC"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (132 commits)
  clk: visconti: pll: initialize clk_init_data to zero
  clk: fsl-sai: Add MCLK generation support
  clk: fsl-sai: Extract clock setup into fsl_sai_clk_register()
  dt-bindings: clock: fsl-sai: Document clock-cells = <1> support
  clk: fsl-sai: Add i.MX8M support with 8 byte register offset
  clk: fsl-sai: Sort the headers
  dt-bindings: clock: fsl-sai: Document i.MX8M support
  clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC
  clk: qcom: rpmh: Add support for Nord rpmh clocks
  clk: qcom: Add TCSR clock driver for Nord SoC
  dt-bindings: clock: qcom: Add Nord Global Clock Controller
  dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs
  dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller
  clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON
  clk: qcom: Constify list of critical CBCR registers
  clk: qcom: Constify qcom_cc_driver_data
  clk: qcom: videocc-glymur: Constify qcom_cc_desc
  clk: qcom: Add a driver for SM8750 GPU clocks
  dt-bindings: clock: qcom: Add SM8750 GPU clocks
  clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support
  ...
parents a85d6ff9 6b701fde
Loading
Loading
Loading
Loading
+5 −1
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ properties:
      - enum:
          - airoha,en7523-scu
          - airoha,en7581-scu
          - econet,en751221-scu

  reg:
    items:
@@ -67,7 +68,9 @@ allOf:
  - if:
      properties:
        compatible:
          const: airoha,en7581-scu
          enum:
            - airoha,en7581-scu
            - econet,en751221-scu
    then:
      properties:
        reg:
@@ -98,3 +101,4 @@ examples:
              #reset-cells = <1>;
      };
    };
+0 −196
Original line number Diff line number Diff line
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Baikal-T1 Clock Control Unit Dividers

maintainers:
  - Serge Semin <fancer.lancer@gmail.com>

description: |
  Clocks Control Unit is the core of Baikal-T1 SoC System Controller
  responsible for the chip subsystems clocking and resetting. The CCU is
  connected with an external fixed rate oscillator, which signal is transformed
  into clocks of various frequencies and then propagated to either individual
  IP-blocks or to groups of blocks (clock domains). The transformation is done
  by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
  later ones are described in this binding. Each clock domain can be also
  individually reset by using the domain clocks divider configuration
  registers. Baikal-T1 CCU is logically divided into the next components:
  1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
     in general can provide any frequency supported by the CCU PLLs).
  2) PLLs clocks generators (PLLs).
  3) AXI-bus clock dividers (AXI) - described in this binding file.
  4) System devices reference clock dividers (SYS) - described in this binding
     file.
  which are connected with each other as shown on the next figure:

          +---------------+
          | Baikal-T1 CCU |
          |   +----+------|- MIPS P5600 cores
          | +-|PLLs|------|- DDR controller
          | | +----+      |
  +----+  | |  |  |       |
  |XTAL|--|-+  |  | +---+-|
  +----+  | |  |  +-|AXI|-|- AXI-bus
          | |  |    +---+-|
          | |  |          |
          | |  +----+---+-|- APB-bus
          | +-------|SYS|-|- Low-speed Devices
          |         +---+-|- High-speed Devices
          +---------------+

  Each sub-block is represented as a separate DT node and has an individual
  driver to be bound with.

  In order to create signals of wide range frequencies the external oscillator
  output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are
  then passed over CCU dividers to create signals required for the target clock
  domain (like AXI-bus or System Device consumers). The dividers have the
  following structure:

          +--------------+
  CLKIN --|->+----+ 1|\  |
  SETCLK--|--|/DIV|->| | |
  CLKDIV--|--|    |  | |-|->CLKLOUT
  LOCK----|--+----+  | | |
          |          |/  |
          |           |  |
  EN------|-----------+  |
  RST-----|--------------|->RSTOUT
          +--------------+

  where CLKIN is the reference clock coming either from CCU PLLs or from an
  external clock oscillator, SETCLK - a command to update the output clock in
  accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of
  the output clock stabilization, EN - enable/disable the divider block,
  RST/RSTOUT - reset clocks domain signal. Depending on the consumer IP-core
  peculiarities the dividers may lack of some functionality depicted on the
  figure above (like EN, CLKDIV/LOCK/SETCLK). In this case the corresponding
  clock provider just doesn't expose either switching functions, or the rate
  configuration, or both of them.

  The clock dividers, which output clock is then consumed by the SoC individual
  devices, are united into a single clocks provider called System Devices CCU.
  Similarly the dividers with output clocks utilized as AXI-bus reference clocks
  are called AXI-bus CCU. Both of them use the common clock bindings with no
  custom properties. The list of exported clocks and reset signals can be found
  in the files: 'include/dt-bindings/clock/bt1-ccu.h' and
  'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU
  are a part of the Baikal-T1 SoC System Controller their DT nodes are supposed
  to be a children of later one.

if:
  properties:
    compatible:
      contains:
        const: baikal,bt1-ccu-axi

then:
  properties:
    clocks:
      items:
        - description: CCU SATA PLL output clock
        - description: CCU PCIe PLL output clock
        - description: CCU Ethernet PLL output clock

    clock-names:
      items:
        - const: sata_clk
        - const: pcie_clk
        - const: eth_clk

else:
  properties:
    clocks:
      items:
        - description: External reference clock
        - description: CCU SATA PLL output clock
        - description: CCU PCIe PLL output clock
        - description: CCU Ethernet PLL output clock

    clock-names:
      items:
        - const: ref_clk
        - const: sata_clk
        - const: pcie_clk
        - const: eth_clk

properties:
  compatible:
    enum:
      - baikal,bt1-ccu-axi
      - baikal,bt1-ccu-sys

  reg:
    maxItems: 1

  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

  clocks:
    minItems: 3
    maxItems: 4

  clock-names:
    minItems: 3
    maxItems: 4

additionalProperties: false

required:
  - compatible
  - "#clock-cells"
  - clocks
  - clock-names

examples:
  # AXI-bus Clock Control Unit node:
  - |
    #include <dt-bindings/clock/bt1-ccu.h>

    clock-controller@1f04d030 {
      compatible = "baikal,bt1-ccu-axi";
      reg = <0x1f04d030 0x030>;
      #clock-cells = <1>;
      #reset-cells = <1>;

      clocks = <&ccu_pll CCU_SATA_PLL>,
               <&ccu_pll CCU_PCIE_PLL>,
               <&ccu_pll CCU_ETH_PLL>;
      clock-names = "sata_clk", "pcie_clk", "eth_clk";
    };
  # System Devices Clock Control Unit node:
  - |
    #include <dt-bindings/clock/bt1-ccu.h>

    clock-controller@1f04d060 {
      compatible = "baikal,bt1-ccu-sys";
      reg = <0x1f04d060 0x0a0>;
      #clock-cells = <1>;
      #reset-cells = <1>;

      clocks = <&clk25m>,
               <&ccu_pll CCU_SATA_PLL>,
               <&ccu_pll CCU_PCIE_PLL>,
               <&ccu_pll CCU_ETH_PLL>;
      clock-names = "ref_clk", "sata_clk", "pcie_clk",
                    "eth_clk";
    };
  # Required Clock Control Unit PLL node:
  - |
    ccu_pll: clock-controller@1f04d000 {
      compatible = "baikal,bt1-ccu-pll";
      reg = <0x1f04d000 0x028>;
      #clock-cells = <1>;

      clocks = <&clk25m>;
      clock-names = "ref_clk";
    };
...
+0 −131
Original line number Diff line number Diff line
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Baikal-T1 Clock Control Unit PLL

maintainers:
  - Serge Semin <fancer.lancer@gmail.com>

description: |
  Clocks Control Unit is the core of Baikal-T1 SoC System Controller
  responsible for the chip subsystems clocking and resetting. The CCU is
  connected with an external fixed rate oscillator, which signal is transformed
  into clocks of various frequencies and then propagated to either individual
  IP-blocks or to groups of blocks (clock domains). The transformation is done
  by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
  It's logically divided into the next components:
  1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
     in general can provide any frequency supported by the CCU PLLs).
  2) PLLs clocks generators (PLLs) - described in this binding file.
  3) AXI-bus clock dividers (AXI).
  4) System devices reference clock dividers (SYS).
  which are connected with each other as shown on the next figure:

          +---------------+
          | Baikal-T1 CCU |
          |   +----+------|- MIPS P5600 cores
          | +-|PLLs|------|- DDR controller
          | | +----+      |
  +----+  | |  |  |       |
  |XTAL|--|-+  |  | +---+-|
  +----+  | |  |  +-|AXI|-|- AXI-bus
          | |  |    +---+-|
          | |  |          |
          | |  +----+---+-|- APB-bus
          | +-------|SYS|-|- Low-speed Devices
          |         +---+-|- High-speed Devices
          +---------------+

  Each CCU sub-block is represented as a separate dts-node and has an
  individual driver to be bound with.

  In order to create signals of wide range frequencies the external oscillator
  output is primarily connected to a set of CCU PLLs. There are five PLLs
  to create a clock for the MIPS P5600 cores, the embedded DDR controller,
  SATA, Ethernet and PCIe domains. The last three domains though named by the
  biggest system interfaces in fact include nearly all of the rest SoC
  peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core
  with an interface wrapper (so called safe PLL' clocks switcher) to simplify
  the PLL configuration procedure. The PLLs work as depicted on the next
  diagram:

      +--------------------------+
      |                          |
      +-->+---+    +---+   +---+ |  +---+   0|\
  CLKF--->|/NF|--->|PFD|...|VCO|-+->|/OD|--->| |
          +---+ +->+---+   +---+ /->+---+    | |--->CLKOUT
  CLKOD---------C----------------+          1| |
       +--------C--------------------------->|/
       |        |                             ^
  Rclk-+->+---+ |                             |
  CLKR--->|/NR|-+                             |
          +---+                               |
  BYPASS--------------------------------------+
  BWADJ--->

  where Rclk is the reference clock coming  from XTAL, NR - reference clock
  divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
  output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
  the binding supports the PLL dividers configuration in accordance with a
  requested rate, while bypassing and bandwidth adjustment settings can be
  added in future if it gets to be necessary.

  The PLLs CLKOUT is then either directly connected with the corresponding
  clocks consumer (like P5600 cores or DDR controller) or passed over a CCU
  divider to create a signal required for the clock domain.

  The CCU PLL dts-node uses the common clock bindings with no custom
  parameters. The list of exported clocks can be found in
  'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the
  Baikal-T1 SoC System Controller its DT node is supposed to be a child of
  later one.

properties:
  compatible:
    const: baikal,bt1-ccu-pll

  reg:
    maxItems: 1

  "#clock-cells":
    const: 1

  clocks:
    description: External reference clock
    maxItems: 1

  clock-names:
    const: ref_clk

additionalProperties: false

required:
  - compatible
  - "#clock-cells"
  - clocks
  - clock-names

examples:
  # Clock Control Unit PLL node:
  - |
    clock-controller@1f04d000 {
      compatible = "baikal,bt1-ccu-pll";
      reg = <0x1f04d000 0x028>;
      #clock-cells = <1>;

      clocks = <&clk25m>;
      clock-names = "ref_clk";
    };
  # Required external oscillator:
  - |
    clk25m: clock-oscillator-25m {
      compatible = "fixed-clock";
      #clock-cells = <0>;
      clock-frequency = <25000000>;
      clock-output-names = "clk25m";
    };
...
+46 −0
Original line number Diff line number Diff line
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/eswin,eic7700-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Eswin EIC7700 SoC clock controller

maintainers:
  - Yifeng Huang <huangyifeng@eswincomputing.com>
  - Xuyang Dong <dongxuyang@eswincomputing.com>

description:
  The clock controller generates and supplies clock to all the modules
  for eic7700 SoC.

properties:
  compatible:
    const: eswin,eic7700-clock

  reg:
    maxItems: 1

  clocks:
    items:
      - description: External 24MHz oscillator clock

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    clock-controller@51828000 {
        compatible = "eswin,eic7700-clock";
        reg = <0x51828000 0x300>;
        clocks = <&xtal24m>;
        #clock-cells = <1>;
    };
+36 −7
Original line number Diff line number Diff line
@@ -10,10 +10,10 @@ maintainers:
  - Michael Walle <michael@walle.cc>

description: |
  It is possible to use the BCLK pin of a SAI module as a generic clock
  output. Some SoC are very constrained in their pin multiplexer
  configuration. Eg. pins can only be changed groups. For example, on the
  LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
  It is possible to use the BCLK or MCLK pin of a SAI module as a generic
  clock output. Some SoC are very constrained in their pin multiplexer
  configuration. E.g. pins can only be changed in groups. For example, on
  the LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
  the second pins are wasted. Using this binding it is possible to use the
  clock of the second SAI as a MCLK clock for an audio codec, for example.

@@ -21,16 +21,45 @@ description: |

properties:
  compatible:
    const: fsl,vf610-sai-clock
    oneOf:
      - items:
          - enum:
              - fsl,imx8mm-sai-clock
              - fsl,imx8mn-sai-clock
              - fsl,imx8mp-sai-clock
          - const: fsl,imx8mq-sai-clock
      - items:
          - enum:
              - fsl,imx8mq-sai-clock
              - fsl,vf610-sai-clock

  reg:
    maxItems: 1

  clocks:
    maxItems: 1
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: bus
      - const: mclk1

  '#clock-cells':
    const: 0
    maximum: 1

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: fsl,vf610-sai-clock
    then:
      properties:
        clocks:
          maxItems: 1
        clock-names: false

required:
  - compatible
Loading