Unverified Commit 6b701fde authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-samsung', 'clk-qcom', 'clk-round', 'clk-sai' and 'clk-cleanup' into clk-next 

* clk-samsung:
  clk: samsung: exynos850: Add APM-to-AP mailbox clock
  dt-bindings: clock: exynos850: Add APM_AP MAILBOX clock
  clk: samsung: Use %pe format to simplify
  clk: samsung: pll: Fix possible truncation in a9fraco recalc rate
  clk: samsung: exynosautov920: add block G3D clock support
  dt-bindings: clock: exynosautov920: add G3D clock definitions
  clk: samsung: gs101: harmonise symbol names (clock arrays)
  clk: samsung: artpec-9: Add initial clock support for ARTPEC-9 SoC
  clk: samsung: Add clock PLL support for ARTPEC-9 SoC
  dt-bindings: clock: Add ARTPEC-9 clock controller

* clk-qcom: (67 commits)
  clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC
  clk: qcom: rpmh: Add support for Nord rpmh clocks
  clk: qcom: Add TCSR clock driver for Nord SoC
  dt-bindings: clock: qcom: Add Nord Global Clock Controller
  dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs
  dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller
  clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON
  clk: qcom: Constify list of critical CBCR registers
  clk: qcom: Constify qcom_cc_driver_data
  clk: qcom: videocc-glymur: Constify qcom_cc_desc
  clk: qcom: Add a driver for SM8750 GPU clocks
  dt-bindings: clock: qcom: Add SM8750 GPU clocks
  clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support
  dt-bindings: clock: qcom: Add CMN PLL support for IPQ8074
  clk: qcom: ipq-cmn-pll: Add IPQ6018 SoC support
  dt-bindings: clock: qcom: Add CMN PLL support for IPQ6018
  clk: qcom: gdsc: Fix error path on registration of multiple pm subdomains
  dt-bindings: clock: qcom: Add missing power-domains property
  clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock
  clk: qcom: dispcc-sc7180: Add missing MDSS resets
  ...

* clk-round:
  clk: divider: remove divider_round_rate() and divider_round_rate_parent()
  clk: divider: remove divider_ro_round_rate_parent()
  clk: remove round_rate() clk ops
  clk: composite: convert from round_rate() to determine_rate()
  clk: test: remove references to clk_ops.round_rate

* clk-sai:
  clk: fsl-sai: Add MCLK generation support
  clk: fsl-sai: Extract clock setup into fsl_sai_clk_register()
  dt-bindings: clock: fsl-sai: Document clock-cells = <1> support
  clk: fsl-sai: Add i.MX8M support with 8 byte register offset
  clk: fsl-sai: Sort the headers
  dt-bindings: clock: fsl-sai: Document i.MX8M support

* clk-cleanup:
  clk: visconti: pll: initialize clk_init_data to zero
  clk: xgene: Fix mapping leak in xgene_pllclk_init()
  clk: Simplify clk_is_match()
  clk: baikal-t1: Remove not-going-to-be-supported code for Baikal SoC
  clk: mvebu: armada-37xx-periph: fix __iomem casts in structure init
  clk: qoriq: avoid format string warning
parents 522a83ab 42ca4f0c 1db4d0ed 7b6894e9 6358c883 1603cbb6

Documentation/devicetree/bindings/clock/axis,artpec9-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/axis,artpec9-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Axis ARTPEC-9 SoC clock controller



maintainers:

  - Jesper Nilsson <jesper.nilsson@axis.com>



description: |

  ARTPEC-9 clock controller is comprised of several CMU (Clock Management Unit)

  units, generating clocks for different domains. Those CMU units are modeled

  as separate device tree nodes, and might depend on each other.

  The root clock in that root tree is an external clock: OSCCLK (25 MHz).

  This external clock must be defined as a fixed-rate clock in dts.



  CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and

  dividers, all other clocks of function blocks (other CMUs) are usually

  derived from CMU_CMU.



  Each clock is assigned an identifier and client nodes can use this identifier

  to specify the clock which they consume. All clocks available for usage

  in clock consumer nodes are defined as preprocessor macros in

  'include/dt-bindings/clock/axis,artpec9-clk.h' header.



properties:

  compatible:

    enum:

      - axis,artpec9-cmu-cmu

      - axis,artpec9-cmu-bus

      - axis,artpec9-cmu-core

      - axis,artpec9-cmu-cpucl

      - axis,artpec9-cmu-fsys0

      - axis,artpec9-cmu-fsys1

      - axis,artpec9-cmu-imem

      - axis,artpec9-cmu-peri



  reg:

    maxItems: 1



  clocks:

    minItems: 1

    maxItems: 5



  clock-names:

    minItems: 1

    maxItems: 5



  "#clock-cells":

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - "#clock-cells"



allOf:

  - if:

      properties:

        compatible:

          const: axis,artpec9-cmu-cmu



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)



        clock-names:

          items:

            - const: fin_pll



  - if:

      properties:

        compatible:

          const: axis,artpec9-cmu-bus



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)

            - description: CMU_BUS bus clock (from CMU_CMU)



        clock-names:

          items:

            - const: fin_pll

            - const: bus



  - if:

      properties:

        compatible:

          const: axis,artpec9-cmu-core



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)

            - description: CMU_CORE main clock (from CMU_CMU)



        clock-names:

          items:

            - const: fin_pll

            - const: main



  - if:

      properties:

        compatible:

          const: axis,artpec9-cmu-cpucl



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)

            - description: CMU_CPUCL switch clock (from CMU_CMU)



        clock-names:

          items:

            - const: fin_pll

            - const: switch



  - if:

      properties:

        compatible:

          const: axis,artpec9-cmu-fsys0



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)

            - description: CMU_FSYS0 bus clock (from CMU_CMU)

            - description: CMU_FSYS0 IP clock (from CMU_CMU)



        clock-names:

          items:

            - const: fin_pll

            - const: bus

            - const: ip



  - if:

      properties:

        compatible:

          const: axis,artpec9-cmu-fsys1



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)

            - description: CMU_FSYS1 scan0 clock (from CMU_CMU)

            - description: CMU_FSYS1 scan1 clock (from CMU_CMU)

            - description: CMU_FSYS1 bus clock (from CMU_CMU)



        clock-names:

          items:

            - const: fin_pll

            - const: scan0

            - const: scan1

            - const: bus



  - if:

      properties:

        compatible:

          const: axis,artpec9-cmu-imem



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)

            - description: CMU_IMEM ACLK clock (from CMU_CMU)

            - description: CMU_IMEM CA5 clock (from CMU_CMU)

            - description: CMU_IMEM JPEG clock (from CMU_CMU)

            - description: CMU_IMEM SSS clock (from CMU_CMU)



        clock-names:

          items:

            - const: fin_pll

            - const: aclk

            - const: ca5

            - const: jpeg

            - const: sss



  - if:

      properties:

        compatible:

          const: axis,artpec9-cmu-peri



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)

            - description: CMU_PERI IP clock (from CMU_CMU)

            - description: CMU_PERI DISP clock (from CMU_CMU)



        clock-names:

          items:

            - const: fin_pll

            - const: ip

            - const: disp



additionalProperties: false



examples:

  # Clock controller node for CMU_FSYS1

  - |

    #include <dt-bindings/clock/axis,artpec9-clk.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        cmu_fsys1: clock-controller@14c10000 {

            compatible = "axis,artpec9-cmu-fsys1";

            reg = <0x0 0x14c10000 0x0 0x4000>;

            #clock-cells = <1>;

            clocks = <&fin_pll>,

                     <&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN0>,

                     <&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN1>,

                     <&cmu_cmu CLK_DOUT_CMU_FSYS1_BUS>;

            clock-names = "fin_pll", "scan0", "scan1", "bus";

        };

    };

...

Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Baikal-T1 Clock Control Unit Dividers



maintainers:

  - Serge Semin <fancer.lancer@gmail.com>



description: |

  Clocks Control Unit is the core of Baikal-T1 SoC System Controller

  responsible for the chip subsystems clocking and resetting. The CCU is

  connected with an external fixed rate oscillator, which signal is transformed

  into clocks of various frequencies and then propagated to either individual

  IP-blocks or to groups of blocks (clock domains). The transformation is done

  by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The

  later ones are described in this binding. Each clock domain can be also

  individually reset by using the domain clocks divider configuration

  registers. Baikal-T1 CCU is logically divided into the next components:

  1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but

     in general can provide any frequency supported by the CCU PLLs).

  2) PLLs clocks generators (PLLs).

  3) AXI-bus clock dividers (AXI) - described in this binding file.

  4) System devices reference clock dividers (SYS) - described in this binding

     file.

  which are connected with each other as shown on the next figure:



          +---------------+

          | Baikal-T1 CCU |

          |   +----+------|- MIPS P5600 cores

          | +-|PLLs|------|- DDR controller

          | | +----+      |

  +----+  | |  |  |       |

  |XTAL|--|-+  |  | +---+-|

  +----+  | |  |  +-|AXI|-|- AXI-bus

          | |  |    +---+-|

          | |  |          |

          | |  +----+---+-|- APB-bus

          | +-------|SYS|-|- Low-speed Devices

          |         +---+-|- High-speed Devices

          +---------------+



  Each sub-block is represented as a separate DT node and has an individual

  driver to be bound with.



  In order to create signals of wide range frequencies the external oscillator

  output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are

  then passed over CCU dividers to create signals required for the target clock

  domain (like AXI-bus or System Device consumers). The dividers have the

  following structure:



          +--------------+

  CLKIN --|->+----+ 1|\  |

  SETCLK--|--|/DIV|->| | |

  CLKDIV--|--|    |  | |-|->CLKLOUT

  LOCK----|--+----+  | | |

          |          |/  |

          |           |  |

  EN------|-----------+  |

  RST-----|--------------|->RSTOUT

          +--------------+



  where CLKIN is the reference clock coming either from CCU PLLs or from an

  external clock oscillator, SETCLK - a command to update the output clock in

  accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of

  the output clock stabilization, EN - enable/disable the divider block,

  RST/RSTOUT - reset clocks domain signal. Depending on the consumer IP-core

  peculiarities the dividers may lack of some functionality depicted on the

  figure above (like EN, CLKDIV/LOCK/SETCLK). In this case the corresponding

  clock provider just doesn't expose either switching functions, or the rate

  configuration, or both of them.



  The clock dividers, which output clock is then consumed by the SoC individual

  devices, are united into a single clocks provider called System Devices CCU.

  Similarly the dividers with output clocks utilized as AXI-bus reference clocks

  are called AXI-bus CCU. Both of them use the common clock bindings with no

  custom properties. The list of exported clocks and reset signals can be found

  in the files: 'include/dt-bindings/clock/bt1-ccu.h' and

  'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU

  are a part of the Baikal-T1 SoC System Controller their DT nodes are supposed

  to be a children of later one.



if:

  properties:

    compatible:

      contains:

        const: baikal,bt1-ccu-axi



then:

  properties:

    clocks:

      items:

        - description: CCU SATA PLL output clock

        - description: CCU PCIe PLL output clock

        - description: CCU Ethernet PLL output clock



    clock-names:

      items:

        - const: sata_clk

        - const: pcie_clk

        - const: eth_clk



else:

  properties:

    clocks:

      items:

        - description: External reference clock

        - description: CCU SATA PLL output clock

        - description: CCU PCIe PLL output clock

        - description: CCU Ethernet PLL output clock



    clock-names:

      items:

        - const: ref_clk

        - const: sata_clk

        - const: pcie_clk

        - const: eth_clk



properties:

  compatible:

    enum:

      - baikal,bt1-ccu-axi

      - baikal,bt1-ccu-sys



  reg:

    maxItems: 1



  "#clock-cells":

    const: 1



  "#reset-cells":

    const: 1



  clocks:

    minItems: 3

    maxItems: 4



  clock-names:

    minItems: 3

    maxItems: 4



additionalProperties: false



required:

  - compatible

  - "#clock-cells"

  - clocks

  - clock-names



examples:

  # AXI-bus Clock Control Unit node:

  - |

    #include <dt-bindings/clock/bt1-ccu.h>



    clock-controller@1f04d030 {

      compatible = "baikal,bt1-ccu-axi";

      reg = <0x1f04d030 0x030>;

      #clock-cells = <1>;

      #reset-cells = <1>;



      clocks = <&ccu_pll CCU_SATA_PLL>,

               <&ccu_pll CCU_PCIE_PLL>,

               <&ccu_pll CCU_ETH_PLL>;

      clock-names = "sata_clk", "pcie_clk", "eth_clk";

    };

  # System Devices Clock Control Unit node:

  - |

    #include <dt-bindings/clock/bt1-ccu.h>



    clock-controller@1f04d060 {

      compatible = "baikal,bt1-ccu-sys";

      reg = <0x1f04d060 0x0a0>;

      #clock-cells = <1>;

      #reset-cells = <1>;



      clocks = <&clk25m>,

               <&ccu_pll CCU_SATA_PLL>,

               <&ccu_pll CCU_PCIE_PLL>,

               <&ccu_pll CCU_ETH_PLL>;

      clock-names = "ref_clk", "sata_clk", "pcie_clk",

                    "eth_clk";

    };

  # Required Clock Control Unit PLL node:

  - |

    ccu_pll: clock-controller@1f04d000 {

      compatible = "baikal,bt1-ccu-pll";

      reg = <0x1f04d000 0x028>;

      #clock-cells = <1>;



      clocks = <&clk25m>;

      clock-names = "ref_clk";

    };

...

Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml

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Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Baikal-T1 Clock Control Unit PLL



maintainers:

  - Serge Semin <fancer.lancer@gmail.com>



description: |

  Clocks Control Unit is the core of Baikal-T1 SoC System Controller

  responsible for the chip subsystems clocking and resetting. The CCU is

  connected with an external fixed rate oscillator, which signal is transformed

  into clocks of various frequencies and then propagated to either individual

  IP-blocks or to groups of blocks (clock domains). The transformation is done

  by means of PLLs and gateable/non-gateable dividers embedded into the CCU.

  It's logically divided into the next components:

  1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but

     in general can provide any frequency supported by the CCU PLLs).

  2) PLLs clocks generators (PLLs) - described in this binding file.

  3) AXI-bus clock dividers (AXI).

  4) System devices reference clock dividers (SYS).

  which are connected with each other as shown on the next figure:



          +---------------+

          | Baikal-T1 CCU |

          |   +----+------|- MIPS P5600 cores

          | +-|PLLs|------|- DDR controller

          | | +----+      |

  +----+  | |  |  |       |

  |XTAL|--|-+  |  | +---+-|

  +----+  | |  |  +-|AXI|-|- AXI-bus

          | |  |    +---+-|

          | |  |          |

          | |  +----+---+-|- APB-bus

          | +-------|SYS|-|- Low-speed Devices

          |         +---+-|- High-speed Devices

          +---------------+



  Each CCU sub-block is represented as a separate dts-node and has an

  individual driver to be bound with.



  In order to create signals of wide range frequencies the external oscillator

  output is primarily connected to a set of CCU PLLs. There are five PLLs

  to create a clock for the MIPS P5600 cores, the embedded DDR controller,

  SATA, Ethernet and PCIe domains. The last three domains though named by the

  biggest system interfaces in fact include nearly all of the rest SoC

  peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core

  with an interface wrapper (so called safe PLL' clocks switcher) to simplify

  the PLL configuration procedure. The PLLs work as depicted on the next

  diagram:



      +--------------------------+

      |                          |

      +-->+---+    +---+   +---+ |  +---+   0|\

  CLKF--->|/NF|--->|PFD|...|VCO|-+->|/OD|--->| |

          +---+ +->+---+   +---+ /->+---+    | |--->CLKOUT

  CLKOD---------C----------------+          1| |

       +--------C--------------------------->|/

       |        |                             ^

  Rclk-+->+---+ |                             |

  CLKR--->|/NR|-+                             |

          +---+                               |

  BYPASS--------------------------------------+

  BWADJ--->



  where Rclk is the reference clock coming  from XTAL, NR - reference clock

  divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -

  output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment

  the binding supports the PLL dividers configuration in accordance with a

  requested rate, while bypassing and bandwidth adjustment settings can be

  added in future if it gets to be necessary.



  The PLLs CLKOUT is then either directly connected with the corresponding

  clocks consumer (like P5600 cores or DDR controller) or passed over a CCU

  divider to create a signal required for the clock domain.



  The CCU PLL dts-node uses the common clock bindings with no custom

  parameters. The list of exported clocks can be found in

  'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the

  Baikal-T1 SoC System Controller its DT node is supposed to be a child of

  later one.



properties:

  compatible:

    const: baikal,bt1-ccu-pll



  reg:

    maxItems: 1



  "#clock-cells":

    const: 1



  clocks:

    description: External reference clock

    maxItems: 1



  clock-names:

    const: ref_clk



additionalProperties: false



required:

  - compatible

  - "#clock-cells"

  - clocks

  - clock-names



examples:

  # Clock Control Unit PLL node:

  - |

    clock-controller@1f04d000 {

      compatible = "baikal,bt1-ccu-pll";

      reg = <0x1f04d000 0x028>;

      #clock-cells = <1>;



      clocks = <&clk25m>;

      clock-names = "ref_clk";

    };

  # Required external oscillator:

  - |

    clk25m: clock-oscillator-25m {

      compatible = "fixed-clock";

      #clock-cells = <0>;

      clock-frequency = <25000000>;

      clock-output-names = "clk25m";

    };

...

Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml

+36 −7
Original line number Diff line number Diff line
@@ -10,10 +10,10 @@ maintainers: 
  - Michael Walle <michael@walle.cc>



description: |

  It is possible to use the BCLK pin of a SAI module as a generic clock

  output. Some SoC are very constrained in their pin multiplexer

  configuration. Eg. pins can only be changed groups. For example, on the

  LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,

  It is possible to use the BCLK or MCLK pin of a SAI module as a generic

  clock output. Some SoC are very constrained in their pin multiplexer

  configuration. E.g. pins can only be changed in groups. For example, on

  the LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,

  the second pins are wasted. Using this binding it is possible to use the

  clock of the second SAI as a MCLK clock for an audio codec, for example.
@@ -21,16 +21,45 @@ description: | 


properties:

  compatible:

    const: fsl,vf610-sai-clock

    oneOf:

      - items:

          - enum:

              - fsl,imx8mm-sai-clock

              - fsl,imx8mn-sai-clock

              - fsl,imx8mp-sai-clock

          - const: fsl,imx8mq-sai-clock

      - items:

          - enum:

              - fsl,imx8mq-sai-clock

              - fsl,vf610-sai-clock



  reg:

    maxItems: 1



  clocks:

    maxItems: 1

    minItems: 1

    maxItems: 2



  clock-names:

    minItems: 1

    items:

      - const: bus

      - const: mclk1



  '#clock-cells':

    const: 0

    maximum: 1



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: fsl,vf610-sai-clock

    then:

      properties:

        clocks:

          maxItems: 1

        clock-names: false



required:

  - compatible

Documentation/devicetree/bindings/clock/qcom,eliza-dispcc.yaml

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Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,eliza-dispcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Display Clock & Reset Controller for Qualcomm Eliza SoC



maintainers:

  - Bjorn Andersson <andersson@kernel.org>

  - Konrad Dybcio <konradybcio@kernel.org>

  - Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>



description: |

  Display clock control module provides the clocks, resets and power

  domains on Qualcomm Eliza SoC platform.



  See also:

  - include/dt-bindings/clock/qcom,eliza-dispcc.h



properties:

  compatible:

    enum:

      - qcom,eliza-dispcc



  clocks:

    items:

      - description: Board XO source

      - description: Board Always On XO source

      - description: Display's AHB clock

      - description: sleep clock

      - description: Byte clock from DSI PHY0

      - description: Pixel clock from DSI PHY0

      - description: Byte clock from DSI PHY1

      - description: Pixel clock from DSI PHY1

      - description: Link clock from DP PHY0

      - description: VCO DIV clock from DP PHY0

      - description: Link clock from DP PHY1

      - description: VCO DIV clock from DP PHY1

      - description: Link clock from DP PHY2

      - description: VCO DIV clock from DP PHY2

      - description: Link clock from DP PHY3

      - description: VCO DIV clock from DP PHY3

      - description: HDMI link clock from HDMI PHY



  power-domains:

    maxItems: 1



  required-opps:

    maxItems: 1



required:

  - compatible

  - clocks

  - '#power-domain-cells'



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>

    #include <dt-bindings/clock/qcom,eliza-gcc.h>

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/power/qcom,rpmhpd.h>

    clock-controller@af00000 {

        compatible = "qcom,eliza-dispcc";

        reg = <0x0af00000 0x20000>;

        clocks = <&bi_tcxo_div2>,

                 <&bi_tcxo_ao_div2>,

                 <&gcc GCC_DISP_AHB_CLK>,

                 <&sleep_clk>,

                 <&dsi0_phy DSI_BYTE_PLL_CLK>,

                 <&dsi0_phy DSI_PIXEL_PLL_CLK>,

                 <&dsi1_phy DSI_BYTE_PLL_CLK>,

                 <&dsi1_phy DSI_PIXEL_PLL_CLK>,

                 <&dp0_phy 0>,

                 <&dp0_phy 1>,

                 <&dp1_phy 0>,

                 <&dp1_phy 1>,

                 <&dp2_phy 0>,

                 <&dp2_phy 1>,

                 <&dp3_phy 0>,

                 <&dp3_phy 1>,

                 <&hdmi_phy>;



        #clock-cells = <1>;

        #power-domain-cells = <1>;

        #reset-cells = <1>;



        power-domains = <&rpmhpd RPMHPD_MMCX>;

        required-opps = <&rpmhpd_opp_low_svs>;

    };

...