Commit 50f4ffac authored by Karol Kolacinski's avatar Karol Kolacinski Committed by Paolo Abeni
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ice: E825C PHY register cleanup 



Minor PTP register refactor, including logical grouping E825C 1-step
timestamping registers. Remove unused register definitions
(PHY_REG_GPCS_BITSLIP, PHY_REG_REVISION).
Also, apply preferred GENMASK macro (instead of ICE_M) for register
fields definition affected by this patch.

Reviewed-by: default avatarSimon Horman <horms@kernel.org>
Reviewed-by: default avatarPrzemek Kitszel <przemyslaw.kitszel@intel.com>
Signed-off-by: default avatarKarol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: default avatarGrzegorz Nitka <grzegorz.nitka@intel.com>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
Link: https://patch.msgid.link/20250310174502.3708121-5-anthony.l.nguyen@intel.com


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent 66a1b7e0

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

+14 −17
Original line number Diff line number Diff line
@@ -780,36 +780,19 @@ static inline bool ice_is_dual(struct ice_hw *hw) 
#define PHY_MAC_XIF_TS_SFD_ENA_M	ICE_M(0x1, 20)

#define PHY_MAC_XIF_GMII_TS_SEL_M	ICE_M(0x1, 21)



/* GPCS config register */

#define PHY_GPCS_CONFIG_REG0		0x268

#define PHY_GPCS_CONFIG_REG0_TX_THR_M	ICE_M(0xF, 24)

#define PHY_GPCS_BITSLIP		0x5C



#define PHY_TS_INT_CONFIG_THRESHOLD_M	ICE_M(0x3F, 0)

#define PHY_TS_INT_CONFIG_ENA_M		BIT(6)



/* 1-step PTP config */

#define PHY_PTP_1STEP_CONFIG		0x270

#define PHY_PTP_1STEP_T1S_UP64_M	ICE_M(0xF, 4)

#define PHY_PTP_1STEP_T1S_DELTA_M	ICE_M(0xF, 8)

#define PHY_PTP_1STEP_PEER_DELAY(_port)	(0x274 + 4 * (_port))

#define PHY_PTP_1STEP_PD_ADD_PD_M	ICE_M(0x1, 0)

#define PHY_PTP_1STEP_PD_DELAY_M	ICE_M(0x3fffffff, 1)

#define PHY_PTP_1STEP_PD_DLY_V_M	ICE_M(0x1, 31)



/* Macros to derive offsets for TimeStampLow and TimeStampHigh */

#define PHY_TSTAMP_L(x) (((x) * 8) + 0)

#define PHY_TSTAMP_U(x) (((x) * 8) + 4)



#define PHY_REG_REVISION		0x85000



#define PHY_REG_DESKEW_0		0x94

#define PHY_REG_DESKEW_0_RLEVEL		GENMASK(6, 0)

#define PHY_REG_DESKEW_0_RLEVEL_FRAC	GENMASK(9, 7)

#define PHY_REG_DESKEW_0_RLEVEL_FRAC_W	3

#define PHY_REG_DESKEW_0_VALID		GENMASK(10, 10)



#define PHY_REG_GPCS_BITSLIP		0x5C

#define PHY_REG_SD_BIT_SLIP(_port_offset)	(0x29C + 4 * (_port_offset))

#define PHY_REVISION_ETH56G		0x10200

#define PHY_VENDOR_TXLANE_THRESH	0x2000C
@@ -829,7 +812,21 @@ static inline bool ice_is_dual(struct ice_hw *hw) 
#define PHY_MAC_BLOCKTIME		0x50

#define PHY_MAC_MARKERTIME		0x54

#define PHY_MAC_TX_OFFSET		0x58

#define PHY_GPCS_BITSLIP		0x5C



#define PHY_PTP_INT_STATUS		0x7FD140



/* ETH56G registers shared per quad */

/* GPCS config register */

#define PHY_GPCS_CONFIG_REG0		0x268

#define PHY_GPCS_CONFIG_REG0_TX_THR_M	GENMASK(27, 24)

/* 1-step PTP config */

#define PHY_PTP_1STEP_CONFIG		0x270

#define PHY_PTP_1STEP_T1S_UP64_M	GENMASK(7, 4)

#define PHY_PTP_1STEP_T1S_DELTA_M	GENMASK(11, 8)

#define PHY_PTP_1STEP_PEER_DELAY(_quad_lane)	(0x274 + 4 * (_quad_lane))

#define PHY_PTP_1STEP_PD_ADD_PD_M	BIT(0)

#define PHY_PTP_1STEP_PD_DELAY_M	GENMASK(30, 1)

#define PHY_PTP_1STEP_PD_DLY_V_M	BIT(31)



#endif /* _ICE_PTP_HW_H_ */