Commit 52199233 authored by Vlad Dogaru's avatar Vlad Dogaru Committed by Paolo Abeni
Browse files

net/mlx5: HWS, Rightsize bwc matcher priority 



The bwc layer was clamping the matcher priority from 32 bits to 16 bits.
This didn't show up until a matcher was resized, since the initial
native matcher was created using the correct 32 bit value.

The fix also reorders fields to avoid some padding.

Fixes: 2111bb97 ("net/mlx5: HWS, added backward-compatible API handling")
Signed-off-by: default avatarVlad Dogaru <vdogaru@nvidia.com>
Reviewed-by: default avatarYevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: default avatarMark Bloch <mbloch@nvidia.com>
Signed-off-by: default avatarTariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1741644104-97767-3-git-send-email-tariqt@nvidia.com


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent 03ebae19

drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h

+1 −1
Original line number Diff line number Diff line
@@ -24,8 +24,8 @@ struct mlx5hws_bwc_matcher { 
	struct mlx5hws_matcher *matcher;

	struct mlx5hws_match_template *mt;

	struct mlx5hws_action_template *at[MLX5HWS_BWC_MATCHER_ATTACH_AT_NUM];

	u32 priority;

	u8 num_of_at;

	u16 priority;

	u8 size_log;

	atomic_t num_of_rules;

	struct list_head *rules;