Unverified Commit 54296aa4 authored by Nitin Gote's avatar Nitin Gote Committed by Rodrigo Vivi
Browse files

drm/i915/gem: fix typos in i915/gem files 



Fix all typos in files under drm/i915/gem reported by codespell tool.

v2: Codespell won't catch it, but it should be
    "user defined" and not "use defined". <Krzysztof Niemiec>

Signed-off-by: default avatarNitin Gote <nitin.r.gote@intel.com>
Reviewed-by: default avatarKrzysztof Niemiec <krzysztof.niemiec@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250120081517.3237326-4-nitin.r.gote@intel.com


Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 61d9f028

drivers/gpu/drm/i915/gem/i915_gem_context.c

+3 −3
Original line number Diff line number Diff line
@@ -238,7 +238,7 @@ static int proto_context_set_persistence(struct drm_i915_private *i915, 
		 *

		 * However, if we cannot reset an engine by itself, we cannot

		 * cleanup a hanging persistent context without causing

		 * colateral damage, and we should not pretend we can by

		 * collateral damage, and we should not pretend we can by

		 * exposing the interface.

		 */

		if (!intel_has_reset_engine(to_gt(i915)))
@@ -1589,7 +1589,7 @@ static int __context_set_persistence(struct i915_gem_context *ctx, bool state) 
		 *

		 * However, if we cannot reset an engine by itself, we cannot

		 * cleanup a hanging persistent context without causing

		 * colateral damage, and we should not pretend we can by

		 * collateral damage, and we should not pretend we can by

		 * exposing the interface.

		 */

		if (!intel_has_reset_engine(to_gt(ctx->i915)))
@@ -2328,7 +2328,7 @@ finalize_create_context_locked(struct drm_i915_file_private *file_priv, 


	/*

	 * One for the xarray and one for the caller.  We need to grab

	 * the reference *prior* to making the ctx visble to userspace

	 * the reference *prior* to making the ctx visible to userspace

	 * in gem_context_register(), as at any point after that

	 * userspace can try to race us with another thread destroying

	 * the context under our feet.

drivers/gpu/drm/i915/gem/i915_gem_context_types.h

+3 −3
Original line number Diff line number Diff line
@@ -245,9 +245,9 @@ struct i915_gem_context { 
	 * Execbuf uses the I915_EXEC_RING_MASK as an index into this

	 * array to select which HW context + engine to execute on. For

	 * the default array, the user_ring_map[] is used to translate

	 * the legacy uABI onto the approprate index (e.g. both

	 * the legacy uABI onto the appropriate index (e.g. both

	 * I915_EXEC_DEFAULT and I915_EXEC_RENDER select the same

	 * context, and I915_EXEC_BSD is weird). For a use defined

	 * context, and I915_EXEC_BSD is weird). For a user defined

	 * array, execbuf uses I915_EXEC_RING_MASK as a plain index.

	 *

	 * User defined by I915_CONTEXT_PARAM_ENGINE (when the
@@ -276,7 +276,7 @@ struct i915_gem_context { 
	 * @vm: unique address space (GTT)

	 *

	 * In full-ppgtt mode, each context has its own address space ensuring

	 * complete seperation of one client from all others.

	 * complete separation of one client from all others.

	 *

	 * In other modes, this is a NULL pointer with the expectation that

	 * the caller uses the shared global GTT.

drivers/gpu/drm/i915/gem/i915_gem_domain.c

+1 −1
Original line number Diff line number Diff line
@@ -276,7 +276,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 
	 * For objects created by userspace through GEM_CREATE with pat_index

	 * set by set_pat extension, simply return 0 here without touching

	 * the cache setting, because such objects should have an immutable

	 * cache setting by desgin and always managed by userspace.

	 * cache setting by design and always managed by userspace.

	 */

	if (i915_gem_object_has_cache_level(obj, cache_level))

		return 0;

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

+2 −2
Original line number Diff line number Diff line
@@ -303,7 +303,7 @@ struct i915_execbuffer { 
	struct intel_gt_buffer_pool_node *batch_pool; /** pool node for batch buffer */



	/**

	 * Indicate either the size of the hastable used to resolve

	 * Indicate either the size of the hashtable used to resolve

	 * relocation handles, or if negative that we are using a direct

	 * index into the execobj[].

	 */
@@ -2543,7 +2543,7 @@ static int eb_pin_timeline(struct i915_execbuffer *eb, struct intel_context *ce, 


			/*

			 * Error path, cannot use intel_context_timeline_lock as

			 * that is user interruptable and this clean up step

			 * that is user interruptible and this clean up step

			 * must be done.

			 */

			mutex_lock(&ce->timeline->mutex);

drivers/gpu/drm/i915/gem/i915_gem_region.c

+1 −1
Original line number Diff line number Diff line
@@ -82,7 +82,7 @@ __i915_gem_object_create_region(struct intel_memory_region *mem, 


	/*

	 * Anything smaller than the min_page_size can't be freely inserted into

	 * the GTT, due to alignemnt restrictions. For such special objects,

	 * the GTT, due to alignment restrictions. For such special objects,

	 * make sure we force memcpy based suspend-resume. In the future we can

	 * revisit this, either by allowing special mis-aligned objects in the

	 * migration path, or by mapping all of LMEM upfront using cheap 1G