Unverified Commit 61d9f028 authored by Nitin Gote's avatar Nitin Gote Committed by Rodrigo Vivi
Browse files

drm/i915/gvt: fix typos in i915/gvt files 



Fix all typos in files under drm/i915/gvt reported by codespell tool.

v2: Correct comment styling. <Krzysztof Niemiec>

Signed-off-by: default avatarNitin Gote <nitin.r.gote@intel.com>
Reviewed-by: default avatarKrzysztof Niemiec <krzysztof.niemiec@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250120081517.3237326-3-nitin.r.gote@intel.com


Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent c156ef57

drivers/gpu/drm/i915/gvt/cmd_parser.c

+8 −7
Original line number Diff line number Diff line
@@ -1906,7 +1906,7 @@ static int perform_bb_shadow(struct parser_exec_state *s) 
		s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;

	unsigned long start_offset = 0;



	/* get the start gm address of the batch buffer */

	/* Get the start gm address of the batch buffer */

	gma = get_gma_bb_from_cmd(s, 1);

	if (gma == INTEL_GVT_INVALID_ADDR)

		return -EFAULT;
@@ -1921,15 +1921,16 @@ static int perform_bb_shadow(struct parser_exec_state *s) 


	bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;



	/* the start_offset stores the batch buffer's start gma's

	 * offset relative to page boundary. so for non-privileged batch

	/*

	 * The start_offset stores the batch buffer's start gma's

	 * offset relative to page boundary. So for non-privileged batch

	 * buffer, the shadowed gem object holds exactly the same page

	 * layout as original gem object. This is for the convience of

	 * layout as original gem object. This is for the convenience of

	 * replacing the whole non-privilged batch buffer page to this

	 * shadowed one in PPGTT at the same gma address. (this replacing

	 * shadowed one in PPGTT at the same gma address. (This replacing

	 * action is not implemented yet now, but may be necessary in

	 * future).

	 * for prileged batch buffer, we just change start gma address to

	 * For prileged batch buffer, we just change start gma address to

	 * that of shadowed page.

	 */

	if (bb->ppgtt)
@@ -1976,7 +1977,7 @@ static int perform_bb_shadow(struct parser_exec_state *s) 
	/*

	 * ip_va saves the virtual address of the shadow batch buffer, while

	 * ip_gma saves the graphics address of the original batch buffer.

	 * As the shadow batch buffer is just a copy from the originial one,

	 * As the shadow batch buffer is just a copy from the original one,

	 * it should be right to use shadow batch buffer'va and original batch

	 * buffer's gma in pair. After all, we don't want to pin the shadow

	 * buffer here (too early).

drivers/gpu/drm/i915/gvt/dmabuf.c

+1 −1
Original line number Diff line number Diff line
@@ -436,7 +436,7 @@ int intel_vgpu_query_plane(struct intel_vgpu *vgpu, void *args) 
			dmabuf_obj_get(dmabuf_obj);

		}

		ret = 0;

		gvt_dbg_dpy("vgpu%d: re-use dmabuf_obj ref %d, id %d\n",

		gvt_dbg_dpy("vgpu%d: reuse dmabuf_obj ref %d, id %d\n",

			    vgpu->id, kref_read(&dmabuf_obj->kref),

			    gfx_plane_info->dmabuf_id);

		mutex_unlock(&vgpu->dmabuf_lock);

drivers/gpu/drm/i915/gvt/edid.c

+1 −1
Original line number Diff line number Diff line
@@ -298,7 +298,7 @@ static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 
	int byte_count = byte_left;

	u32 reg_data = 0;



	/* Data can only be recevied if previous settings correct */

	/* Data can only be received if previous settings correct */

	if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {

		if (byte_left <= 0) {

			memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);

drivers/gpu/drm/i915/gvt/gtt.c

+1 −1
Original line number Diff line number Diff line
@@ -1193,7 +1193,7 @@ static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu, 
		gvt_vdbg_mm("shadow 64K gtt entry\n");

		/*

		 * The layout of 64K page is special, the page size is

		 * controlled by uper PDE. To be simple, we always split

		 * controlled by upper PDE. To be simple, we always split

		 * 64K page to smaller 4K pages in shadow PT.

		 */

		return split_64KB_gtt_entry(vgpu, spt, index, &se);

drivers/gpu/drm/i915/gvt/gvt.h

+5 −3
Original line number Diff line number Diff line
@@ -452,8 +452,10 @@ void intel_vgpu_free_resource(struct intel_vgpu *vgpu); 
void intel_vgpu_write_fence(struct intel_vgpu *vgpu,

	u32 fence, u64 value);



/* Macros for easily accessing vGPU virtual/shadow register.

   Explicitly seperate use for typed MMIO reg or real offset.*/

/*

 * Macros for easily accessing vGPU virtual/shadow register.

 * Explicitly separate use for typed MMIO reg or real offset.

 */

#define vgpu_vreg_t(vgpu, reg) \

	(*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))

#define vgpu_vreg(vgpu, offset) \
@@ -696,7 +698,7 @@ static inline void intel_gvt_mmio_set_cmd_write_patch( 
 * @offset: register offset

 *

 * Returns:

 * True if GPU commmand write to an MMIO should be patched

 * True if GPU command write to an MMIO should be patched.

 */

static inline bool intel_gvt_mmio_is_cmd_write_patch(

			struct intel_gvt *gvt, unsigned int offset)