Commit 560c98b4 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Rob Clark
Browse files

drm/msm/a6xx: Get a handle to the common UBWC config



Start the great despaghettification by getting a pointer to the common
UBWC configuration, which houses e.g. UBWC versions that we need to
make decisions.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/660965/


Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
parent 45a29741
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+14 −2
Original line number Diff line number Diff line
@@ -604,8 +604,13 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
	gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]);
}

static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
{
	/* Inherit the common config and make some necessary fixups */
	gpu->common_ubwc_cfg = qcom_ubwc_config_get_data();
	if (IS_ERR(gpu->common_ubwc_cfg))
		return PTR_ERR(gpu->common_ubwc_cfg);

	gpu->ubwc_config.rgb565_predicator = 0;
	gpu->ubwc_config.uavflagprd_inv = 0;
	gpu->ubwc_config.min_acc_len = 0;
@@ -682,6 +687,8 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
		gpu->ubwc_config.highest_bank_bit = 14;
		gpu->ubwc_config.min_acc_len = 1;
	}

	return 0;
}

static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
@@ -2563,7 +2570,12 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
	msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu,
				  a6xx_fault_handler);

	a6xx_calc_ubwc_config(adreno_gpu);
	ret = a6xx_calc_ubwc_config(adreno_gpu);
	if (ret) {
		a6xx_destroy(&(a6xx_gpu->base.base));
		return ERR_PTR(ret);
	}

	/* Set up the preemption specific bits and pieces for each ringbuffer */
	a6xx_preempt_init(gpu);

+3 −0
Original line number Diff line number Diff line
@@ -12,6 +12,8 @@
#include <linux/firmware.h>
#include <linux/iopoll.h>

#include <linux/soc/qcom/ubwc.h>

#include "msm_gpu.h"

#include "adreno_common.xml.h"
@@ -242,6 +244,7 @@ struct adreno_gpu {
		 */
		u32 macrotile_mode;
	} ubwc_config;
	const struct qcom_ubwc_cfg_data *common_ubwc_cfg;

	/*
	 * Register offsets are different between some GPUs.