Commit 5682cd86 authored by Jiadong Zhu's avatar Jiadong Zhu Committed by Alex Deucher
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drm/amdgpu/sdma5.2: implement ring reset callback for sdma5.2 



Implement sdma queue reset callback via MMIO.

v2: enter/exit safemode for mmio queue reset.

Signed-off-by: default avatarJiadong Zhu <Jiadong.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1fd7c37e

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

+91 −0
Original line number Diff line number Diff line
@@ -1445,6 +1445,96 @@ static int sdma_v5_2_wait_for_idle(void *handle) 
	return -ETIMEDOUT;

}



static int sdma_v5_2_reset_queue(struct amdgpu_ring *ring, unsigned int vmid)

{

	struct amdgpu_device *adev = ring->adev;

	int i, j, r;

	u32 rb_cntl, ib_cntl, f32_cntl, freeze, cntl, preempt, soft_reset, stat1_reg;



	if (amdgpu_sriov_vf(adev))

		return -EINVAL;



	for (i = 0; i < adev->sdma.num_instances; i++) {

		if (ring == &adev->sdma.instance[i].ring)

			break;

	}



	if (i == adev->sdma.num_instances) {

		DRM_ERROR("sdma instance not found\n");

		return -EINVAL;

	}



	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);



	/* stop queue */

	ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));

	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);

	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);



	rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));

	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);

	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);



	/*engine stop SDMA1_F32_CNTL.HALT to 1 and SDMAx_FREEZE freeze bit to 1 */

	freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE));

	freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 1);

	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze);



	for (j = 0; j < adev->usec_timeout; j++) {

		freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE));



		if (REG_GET_FIELD(freeze, SDMA0_FREEZE, FROZEN) & 1)

			break;

		udelay(1);

	}





	if (j == adev->usec_timeout) {

		stat1_reg = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS1_REG));

		if ((stat1_reg & 0x3FF) != 0x3FF) {

			DRM_ERROR("cannot soft reset as sdma not idle\n");

			r = -ETIMEDOUT;

			goto err0;

		}

	}



	f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));

	f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);

	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);



	cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));

	cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0);

	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), cntl);



	/* soft reset SDMA_GFX_PREEMPT.IB_PREEMPT = 0 mmGRBM_SOFT_RESET.SOFT_RESET_SDMA0/1 = 1 */

	preempt = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_PREEMPT));

	preempt = REG_SET_FIELD(preempt, SDMA0_GFX_PREEMPT, IB_PREEMPT, 0);

	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_PREEMPT), preempt);



	soft_reset = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

	soft_reset |= 1 << GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT << i;





	WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, soft_reset);



	udelay(50);



	soft_reset &= ~(1 << GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT << i);



	WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, soft_reset);



	/* unfreeze and unhalt */

	freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE));

	freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0);

	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze);



	r = sdma_v5_2_gfx_resume_instance(adev, i, true);



err0:

	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);

	return r;

}



static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)

{

	int i, r = 0;
@@ -1880,6 +1970,7 @@ static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = { 
	.emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,

	.init_cond_exec = sdma_v5_2_ring_init_cond_exec,

	.preempt_ib = sdma_v5_2_ring_preempt_ib,

	.reset = sdma_v5_2_reset_queue,

};



static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)