Commit 57b55c76 authored by Yu Tu's avatar Yu Tu Committed by Jerome Brunet
Browse files

clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller 



Add the peripherals clock controller driver in the S4 SoC family.

[jbrunet: remove extra new line at end of s4-peripherals.h]
Signed-off-by: default avatarYu Tu <yu.tu@amlogic.com>
Link: https://lore.kernel.org/r/20230904075504.23263-5-yu.tu@amlogic.com


Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent e787c9c5

drivers/clk/meson/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -156,4 +156,15 @@ config COMMON_CLK_S4_PLL 
	  Support for the PLL clock controller on Amlogic S805X2 and S905Y4 devices,

	  AKA S4. Say Y if you want the board to work, because PLLs are the parent of

	  most peripherals.



config COMMON_CLK_S4_PERIPHERALS

	tristate "S4 SoC peripherals clock controllers support"

	depends on ARM64

	default y

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_DUALDIV

	select COMMON_CLK_MESON_VID_PLL_DIV

	help

	  Support for the peripherals clock controller on Amlogic S805X2 and S905Y4

	  devices, AKA S4. Say Y if you want S4 peripherals clock controller to work.

endmenu

drivers/clk/meson/Makefile

+1 −0
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@@ -23,3 +23,4 @@ obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o 
obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o

obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o

obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o

obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o

drivers/clk/meson/s4-peripherals.c

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+3813 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/clk/meson/s4-peripherals.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */

/*

 * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved

 * Author: Yu Tu <yu.tu@amlogic.com>

 */



#ifndef __MESON_S4_PERIPHERALS_H__

#define __MESON_S4_PERIPHERALS_H__



#define CLKCTRL_RTC_BY_OSCIN_CTRL0                 0x008

#define CLKCTRL_RTC_BY_OSCIN_CTRL1                 0x00c

#define CLKCTRL_RTC_CTRL                           0x010

#define CLKCTRL_SYS_CLK_CTRL0                      0x040

#define CLKCTRL_SYS_CLK_EN0_REG0                   0x044

#define CLKCTRL_SYS_CLK_EN0_REG1                   0x048

#define CLKCTRL_SYS_CLK_EN0_REG2                   0x04c

#define CLKCTRL_SYS_CLK_EN0_REG3                   0x050

#define CLKCTRL_CECA_CTRL0                         0x088

#define CLKCTRL_CECA_CTRL1                         0x08c

#define CLKCTRL_CECB_CTRL0                         0x090

#define CLKCTRL_CECB_CTRL1                         0x094

#define CLKCTRL_SC_CLK_CTRL                        0x098

#define CLKCTRL_CLK12_24_CTRL                      0x0a8

#define CLKCTRL_VID_CLK_CTRL                       0x0c0

#define CLKCTRL_VID_CLK_CTRL2                      0x0c4

#define CLKCTRL_VID_CLK_DIV                        0x0c8

#define CLKCTRL_VIID_CLK_DIV                       0x0cc

#define CLKCTRL_VIID_CLK_CTRL                      0x0d0

#define CLKCTRL_HDMI_CLK_CTRL                      0x0e0

#define CLKCTRL_VID_PLL_CLK_DIV                    0x0e4

#define CLKCTRL_VPU_CLK_CTRL                       0x0e8

#define CLKCTRL_VPU_CLKB_CTRL                      0x0ec

#define CLKCTRL_VPU_CLKC_CTRL                      0x0f0

#define CLKCTRL_VID_LOCK_CLK_CTRL                  0x0f4

#define CLKCTRL_VDIN_MEAS_CLK_CTRL                 0x0f8

#define CLKCTRL_VAPBCLK_CTRL                       0x0fc

#define CLKCTRL_HDCP22_CTRL                        0x100

#define CLKCTRL_VDEC_CLK_CTRL                      0x140

#define CLKCTRL_VDEC2_CLK_CTRL                     0x144

#define CLKCTRL_VDEC3_CLK_CTRL                     0x148

#define CLKCTRL_VDEC4_CLK_CTRL                     0x14c

#define CLKCTRL_TS_CLK_CTRL                        0x158

#define CLKCTRL_MALI_CLK_CTRL                      0x15c

#define CLKCTRL_NAND_CLK_CTRL                      0x168

#define CLKCTRL_SD_EMMC_CLK_CTRL                   0x16c

#define CLKCTRL_SPICC_CLK_CTRL                     0x174

#define CLKCTRL_GEN_CLK_CTRL                       0x178

#define CLKCTRL_SAR_CLK_CTRL                       0x17c

#define CLKCTRL_PWM_CLK_AB_CTRL                    0x180

#define CLKCTRL_PWM_CLK_CD_CTRL                    0x184

#define CLKCTRL_PWM_CLK_EF_CTRL                    0x188

#define CLKCTRL_PWM_CLK_GH_CTRL                    0x18c

#define CLKCTRL_PWM_CLK_IJ_CTRL                    0x190

#define CLKCTRL_DEMOD_CLK_CTRL                     0x200



#endif /* __MESON_S4_PERIPHERALS_H__ */