Merge branch 'for-v6.12/clk-dt-bindings' into next/clk

#define CLK_GOUT_FSYS_MMC_EMBD		58

#define CLK_GOUT_FSYS_MMC_SDIO		59

#define CLK_GOUT_FSYS_USB30DRD		60

#define CLK_MOUT_SHARED0_PLL		61

#define CLK_MOUT_SHARED1_PLL		62

/* CMU_CORE */

#define CLK_MOUT_CORE_BUS_USER			1

#define CLK_MOUT_FSYS_MMC_CARD_USER		2

#define CLK_MOUT_FSYS_MMC_EMBD_USER		3

#define CLK_MOUT_FSYS_MMC_SDIO_USER		4

#define CLK_MOUT_FSYS_USB30DRD_USER	4

#define CLK_GOUT_MMC_CARD_ACLK			5

#define CLK_GOUT_MMC_CARD_SDCLKIN		6

#define CLK_GOUT_MMC_EMBD_ACLK			7

#define CLK_GOUT_MMC_EMBD_SDCLKIN		8

#define CLK_GOUT_MMC_SDIO_ACLK			9

#define CLK_GOUT_MMC_SDIO_SDCLKIN		10

#define CLK_MOUT_FSYS_USB30DRD_USER		11

#define CLK_MOUT_USB_PLL			12

#define CLK_FOUT_USB_PLL			13

#define CLK_FSYS_USB20PHY_CLKCORE		14

#define CLK_FSYS_USB30DRD_ACLK_20PHYCTRL	15

#define CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_0	16

#define CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_1	17

#define CLK_FSYS_USB30DRD_BUS_CLK_EARLY		18

#define CLK_FSYS_USB30DRD_REF_CLK		19

#endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */