Commit b9dee49c authored by David Virag's avatar David Virag Committed by Krzysztof Kozlowski
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dt-bindings: clock: exynos7885: Add indices for USB clocks 



Exynos7885 SoC has a DWC3 USB Controller with Exynos USB PHY which in
theory supports USB3 SuperSpeed, but is only used as USB2 in all known
devices.

These, of course, need some clocks.
Add indices for these clocks.

Signed-off-by: default avatarDavid Virag <virag.david003@gmail.com>
Link: https://lore.kernel.org/r/20240806121157.479212-4-virag.david003@gmail.com


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 59baa83e

include/dt-bindings/clock/exynos7885.h

+19 −11
Original line number Diff line number Diff line
@@ -145,5 +145,13 @@ 
#define CLK_GOUT_MMC_SDIO_ACLK			9

#define CLK_GOUT_MMC_SDIO_SDCLKIN		10

#define CLK_MOUT_FSYS_USB30DRD_USER		11

#define CLK_MOUT_USB_PLL			12

#define CLK_FOUT_USB_PLL			13

#define CLK_FSYS_USB20PHY_CLKCORE		14

#define CLK_FSYS_USB30DRD_ACLK_20PHYCTRL	15

#define CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_0	16

#define CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_1	17

#define CLK_FSYS_USB30DRD_BUS_CLK_EARLY		18

#define CLK_FSYS_USB30DRD_REF_CLK		19



#endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */