Commit 589eb114 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-qcom', 'clk-rockchip', 'clk-sophgo' and 'clk-thead' into clk-next

 - Add support for the AP sub-system clock controller in the T-Head TH1520

* clk-qcom: (71 commits)
  clk: qcom: Park shared RCGs upon registration
  clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks
  clk: qcom: common: Add interconnect clocks support
  interconnect: icc-clk: Add devm_icc_clk_register
  interconnect: icc-clk: Specify master/slave ids
  dt-bindings: clock: qcom: Add AHB clock for SM8150
  clk: qcom: gcc-x1e80100: Set parent rate for USB3 sec and tert PHY pipe clks
  dt-bindings: interconnect: Add Qualcomm IPQ9574 support
  clk: qcom: kpss-xcc: Return of_clk_add_hw_provider to transfer the error
  clk: qcom: lpasscc-sc8280xp: Constify struct regmap_config
  clk: qcom: gcc-x1e80100: Fix halt_check for all pipe clocks
  clk: qcom: gcc-ipq6018: update sdcc max clock frequency
  clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driver
  dt-bindings: clock: qcom: Add SM8650 camera clock controller
  dt-bindings: clock: qcom: Update the order of SC8280XP camcc header
  clk: qcom: videocc-sm8550: Add SM8650 video clock controller
  clk: qcom: videocc-sm8550: Add support for videocc XO clk ares
  dt-bindings: clock: qcom: Add SM8650 video clock controller
  dt-bindings: clock: qcom: Update SM8450 videocc header file name
  clk: qcom: gpucc-sa8775p: Update wait_val fields for GPU GDSC's
  ...

* clk-rockchip:
  dt-bindings: clock: rk3188-cru-common: remove CLK_NR_CLKS
  clk: rockchip: rk3188: Drop CLK_NR_CLKS usage
  clk: rockchip: Switch to use kmemdup_array()
  clk: rockchip: rk3128: Add HCLK_SFC
  dt-bindings: clock: rk3128: Add HCLK_SFC
  dt-bindings: clock: rk3128: Drop CLK_NR_CLKS
  clk: rockchip: rk3128: Drop CLK_NR_CLKS usage
  clk: rockchip: rk3128: Add hclk_vio_h2p to critical clocks
  clk: rockchip: rk3128: Export PCLK_MIPIPHY
  dt-bindings: clock: rk3128: Add PCLK_MIPIPHY

* clk-sophgo:
  clk: sophgo: Avoid -Wsometimes-uninitialized in sg2042_clk_pll_set_rate()
  clk/sophgo: Using BUG() instead of unreachable() in mmux_get_parent_id()
  clk: sophgo: Add SG2042 clock driver
  dt-bindings: clock: sophgo: add clkgen for SG2042
  dt-bindings: clock: sophgo: add RP gate clocks for SG2042
  dt-bindings: clock: sophgo: add pll clocks for SG2042

* clk-thead:
  clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks
  dt-bindings: clock: Document T-Head TH1520 AP_SUBSYS controller
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+4 −16
Original line number Diff line number Diff line
@@ -40,31 +40,19 @@ properties:
      - description: DSI 1 PLL byte clock
      - description: DSI 1 PLL DSI clock

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

  power-domains:
    items:
      - description: MMCX power domain

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false
allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
+4 −16
Original line number Diff line number Diff line
@@ -37,28 +37,16 @@ properties:
      - const: dp_phy_pll_link_clk
      - const: dp_phy_pll_vco_div_clk

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false
allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
+30 −16
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ properties:
      - qcom,sm8350-dispcc

  clocks:
    minItems: 7
    items:
      - description: Board XO source
      - description: Byte clock from DSI PHY0
@@ -35,8 +36,15 @@ properties:
      - description: Pixel clock from DSI PHY1
      - description: Link clock from DP PHY
      - description: VCO DIV clock from DP PHY
      - description: Link clock from eDP PHY
      - description: VCO DIV clock from eDP PHY
      - description: Link clock from DP1 PHY
      - description: VCO DIV clock from DP1 PHY
      - description: Link clock from DP2 PHY
      - description: VCO DIV clock from DP2 PHY

  clock-names:
    minItems: 7
    items:
      - const: bi_tcxo
      - const: dsi0_phy_pll_out_byteclk
@@ -45,18 +53,12 @@ properties:
      - const: dsi1_phy_pll_out_dsiclk
      - const: dp_phy_pll_link_clk
      - const: dp_phy_pll_vco_div_clk

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1
      - const: edp_phy_pll_link_clk
      - const: edp_phy_pll_vco_div_clk
      - const: dptx1_phy_pll_link_clk
      - const: dptx1_phy_pll_vco_div_clk
      - const: dptx2_phy_pll_link_clk
      - const: dptx2_phy_pll_vco_div_clk

  power-domains:
    description:
@@ -70,14 +72,26 @@ properties:

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false
allOf:
  - $ref: qcom,gcc.yaml#
  - if:
      not:
        properties:
          compatible:
            contains:
              const: qcom,sc8180x-dispcc
    then:
      properties:
        clocks:
          maxItems: 7
        clock-names:
          maxItems: 7

unevaluatedProperties: false

examples:
  - |
+2 −1
Original line number Diff line number Diff line
@@ -69,6 +69,8 @@ properties:
    const: 1
    deprecated: true

  '#power-domain-cells': false

required:
  - compatible

@@ -81,7 +83,6 @@ examples:
      reg = <0x00900000 0x4000>;
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;

      thermal-sensor {
        compatible = "qcom,msm8960-tsens";
+1 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ properties:

required:
  - compatible
  - '#power-domain-cells'

unevaluatedProperties: false

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