Commit bc060e6b authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-renesas', 'clk-amlogic', 'clk-allwinner' and 'clk-samsung' into clk-next 

* clk-renesas:
  clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C
  clk: renesas: r8a779h0: Add Audio clocks
  clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP
  dt-bindings: clock: rcar-gen2: Remove obsolete header files
  dt-bindings: clock: r8a7779: Remove duplicate newline
  clk: renesas: Drop "Renesas" from individual driver descriptions
  clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in comments
  clk: renesas: r8a779h0: Add VIN clocks
  dt-bindings: clock: renesas,rzg2l-cpg: Update description for #reset-cells
  clk: renesas: rcar-gen2: Use DEFINE_SPINLOCK() for static spinlock
  clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlock
  clk: renesas: r8a77970: Use common cpg_lock
  clk: renesas: r8a779h0: Add CSI-2 clocks
  clk: renesas: r8a779h0: Add ISPCS clocks

* clk-amlogic:
  clk: meson: add missing MODULE_DESCRIPTION() macros
  dt-bindings: clock: meson: a1: peripherals: support sys_pll input
  dt-bindings: clock: meson: a1: pll: introduce new syspll bindings
  clk: meson: add 'NOINIT_ENABLED' flag to eliminate init for enabled PLL
  clk: meson: c3: add c3 clock peripherals controller driver
  clk: meson: c3: add support for the C3 SoC PLL clock
  dt-bindings: clock: add Amlogic C3 peripherals clock controller
  dt-bindings: clock: add Amlogic C3 SCMI clock controller support
  dt-bindings: clock: add Amlogic C3 PLL clock controller
  dt-bindings: clock: meson: Convert axg-audio-clkc to YAML format
  clk: meson: s4: fix pwm_j_div parent clock
  clk: meson: s4: fix fixed_pll_dco clock

* clk-allwinner:
  clk: sunxi-ng r40: Constify struct regmap_config
  clk: sunxi-ng: h616: Add clock/reset for GPADC
  dt-bindings: clock: sun50i-h616-ccu: Add GPADC clocks
  clk: sunxi: Remove unused struct 'gates_data'
  clk: sunxi-ng: add missing MODULE_DESCRIPTION() macros

* clk-samsung:
  clk: samsung: gs101: mark gout_hsi2_ufs_embd_i_clk_unipro as critical
  clk: samsung: Switch to use kmemdup_array()
  clk: samsung: exynos-clkout: Remove misleading of_match_table/MODULE_DEVICE_TABLE
parents 160d7b9f e96b0420 d424c029 38bded81 b1da66d2

Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml

+7 −2
Original line number Diff line number Diff line
@@ -30,6 +30,8 @@ properties: 
      - description: input fixed pll div7

      - description: input hifi pll

      - description: input oscillator (usually at 24MHz)

      - description: input sys pll

    minItems: 6 # sys_pll is optional



  clock-names:

    items:
@@ -39,6 +41,8 @@ properties: 
      - const: fclk_div7

      - const: hifi_pll

      - const: xtal

      - const: sys_pll

    minItems: 6 # sys_pll is optional



required:

  - compatible
@@ -65,9 +69,10 @@ examples: 
                     <&clkc_pll CLKID_FCLK_DIV5>,

                     <&clkc_pll CLKID_FCLK_DIV7>,

                     <&clkc_pll CLKID_HIFI_PLL>,

                     <&xtal>;

                     <&xtal>,

                     <&clkc_pll CLKID_SYS_PLL>;

            clock-names = "fclk_div2", "fclk_div3",

                          "fclk_div5", "fclk_div7",

                          "hifi_pll", "xtal";

                          "hifi_pll", "xtal", "sys_pll";

        };

    };

Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml

+7 −2
Original line number Diff line number Diff line
@@ -26,11 +26,15 @@ properties: 
    items:

      - description: input fixpll_in

      - description: input hifipll_in

      - description: input syspll_in

    minItems: 2 # syspll_in is optional



  clock-names:

    items:

      - const: fixpll_in

      - const: hifipll_in

      - const: syspll_in

    minItems: 2 # syspll_in is optional



required:

  - compatible
@@ -53,7 +57,8 @@ examples: 
            reg = <0 0x7c80 0 0x18c>;

            #clock-cells = <1>;

            clocks = <&clkc_periphs CLKID_FIXPLL_IN>,

                     <&clkc_periphs CLKID_HIFIPLL_IN>;

            clock-names = "fixpll_in", "hifipll_in";

                     <&clkc_periphs CLKID_HIFIPLL_IN>,

                     <&clkc_periphs CLKID_SYSPLL_IN>;

            clock-names = "fixpll_in", "hifipll_in", "syspll_in";

        };

    };

Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt

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+0 −59
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* Amlogic AXG Audio Clock Controllers



The Amlogic AXG audio clock controller generates and supplies clock to the

other elements of the audio subsystem, such as fifos, i2s, spdif and pdm

devices.



Required Properties:



- compatible	: should be "amlogic,axg-audio-clkc" for the A113X and A113D,

		  "amlogic,g12a-audio-clkc" for G12A,

		  "amlogic,sm1-audio-clkc" for S905X3.

- reg		: physical base address of the clock controller and length of

		  memory mapped region.

- clocks	: a list of phandle + clock-specifier pairs for the clocks listed

		  in clock-names.

- clock-names	: must contain the following:

		  * "pclk" - Main peripheral bus clock

		  may contain the following:

		  * "mst_in[0-7]" - 8 input plls to generate clock signals

		  * "slv_sclk[0-9]" - 10 slave bit clocks provided by external

				      components.

		  * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external

				       components.

- resets	: phandle of the internal reset line

- #clock-cells	: should be 1.

- #reset-cells  : should be 1 on the g12a (and following) soc family



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. All available clocks are defined as

preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be

used in device tree sources.



Example:



clkc_audio: clock-controller@0 {

	compatible = "amlogic,axg-audio-clkc";

	reg = <0x0 0x0 0x0 0xb4>;

	#clock-cells = <1>;



	clocks = <&clkc CLKID_AUDIO>,

		 <&clkc CLKID_MPLL0>,

		 <&clkc CLKID_MPLL1>,

		 <&clkc CLKID_MPLL2>,

		 <&clkc CLKID_MPLL3>,

		 <&clkc CLKID_HIFI_PLL>,

		 <&clkc CLKID_FCLK_DIV3>,

		 <&clkc CLKID_FCLK_DIV4>,

		 <&clkc CLKID_GP0_PLL>;

	clock-names = "pclk",

		      "mst_in0",

		      "mst_in1",

		      "mst_in2",

		      "mst_in3",

		      "mst_in4",

		      "mst_in5",

		      "mst_in6",

		      "mst_in7";

	resets = <&reset RESET_AUDIO>;

};

Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic AXG Audio Clock Controller



maintainers:

  - Neil Armstrong <neil.armstrong@linaro.org>

  - Jerome Brunet <jbrunet@baylibre.com>



description:

  The Amlogic AXG audio clock controller generates and supplies clock to the

  other elements of the audio subsystem, such as fifos, i2s, spdif and pdm

  devices.



properties:

  compatible:

    enum:

      - amlogic,axg-audio-clkc

      - amlogic,g12a-audio-clkc

      - amlogic,sm1-audio-clkc



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  reg:

    maxItems: 1



  clocks:

    minItems: 1

    items:

      - description: main peripheral bus clock

      - description: input plls to generate clock signals N0

      - description: input plls to generate clock signals N1

      - description: input plls to generate clock signals N2

      - description: input plls to generate clock signals N3

      - description: input plls to generate clock signals N4

      - description: input plls to generate clock signals N5

      - description: input plls to generate clock signals N6

      - description: input plls to generate clock signals N7

      - description: slave bit clock N0 provided by external components

      - description: slave bit clock N1 provided by external components

      - description: slave bit clock N2 provided by external components

      - description: slave bit clock N3 provided by external components

      - description: slave bit clock N4 provided by external components

      - description: slave bit clock N5 provided by external components

      - description: slave bit clock N6 provided by external components

      - description: slave bit clock N7 provided by external components

      - description: slave bit clock N8 provided by external components

      - description: slave bit clock N9 provided by external components

      - description: slave sample clock N0 provided by external components

      - description: slave sample clock N1 provided by external components

      - description: slave sample clock N2 provided by external components

      - description: slave sample clock N3 provided by external components

      - description: slave sample clock N4 provided by external components

      - description: slave sample clock N5 provided by external components

      - description: slave sample clock N6 provided by external components

      - description: slave sample clock N7 provided by external components

      - description: slave sample clock N8 provided by external components

      - description: slave sample clock N9 provided by external components



  clock-names:

    minItems: 1

    items:

      - const: pclk

      - const: mst_in0

      - const: mst_in1

      - const: mst_in2

      - const: mst_in3

      - const: mst_in4

      - const: mst_in5

      - const: mst_in6

      - const: mst_in7

      - const: slv_sclk0

      - const: slv_sclk1

      - const: slv_sclk2

      - const: slv_sclk3

      - const: slv_sclk4

      - const: slv_sclk5

      - const: slv_sclk6

      - const: slv_sclk7

      - const: slv_sclk8

      - const: slv_sclk9

      - const: slv_lrclk0

      - const: slv_lrclk1

      - const: slv_lrclk2

      - const: slv_lrclk3

      - const: slv_lrclk4

      - const: slv_lrclk5

      - const: slv_lrclk6

      - const: slv_lrclk7

      - const: slv_lrclk8

      - const: slv_lrclk9



  resets:

    description: internal reset line



required:

  - compatible

  - '#clock-cells'

  - reg

  - clocks

  - clock-names

  - resets



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - amlogic,g12a-audio-clkc

              - amlogic,sm1-audio-clkc

    then:

      required:

        - '#reset-cells'

    else:

      properties:

        '#reset-cells': false



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/axg-clkc.h>

    #include <dt-bindings/reset/amlogic,meson-axg-reset.h>

    apb {

        #address-cells = <2>;

        #size-cells = <2>;



        clkc_audio: clock-controller@0 {

            compatible = "amlogic,axg-audio-clkc";

            reg = <0x0 0x0 0x0 0xb4>;

            #clock-cells = <1>;



            clocks = <&clkc CLKID_AUDIO>,

                     <&clkc CLKID_MPLL0>,

                     <&clkc CLKID_MPLL1>,

                     <&clkc CLKID_MPLL2>,

                     <&clkc CLKID_MPLL3>,

                     <&clkc CLKID_HIFI_PLL>,

                     <&clkc CLKID_FCLK_DIV3>,

                     <&clkc CLKID_FCLK_DIV4>,

                     <&clkc CLKID_GP0_PLL>,

                     <&slv_sclk0>,

                     <&slv_sclk1>,

                     <&slv_sclk2>,

                     <&slv_sclk3>,

                     <&slv_sclk4>,

                     <&slv_sclk5>,

                     <&slv_sclk6>,

                     <&slv_sclk7>,

                     <&slv_sclk8>,

                     <&slv_sclk9>,

                     <&slv_lrclk0>,

                     <&slv_lrclk1>,

                     <&slv_lrclk2>,

                     <&slv_lrclk3>,

                     <&slv_lrclk4>,

                     <&slv_lrclk5>,

                     <&slv_lrclk6>,

                     <&slv_lrclk7>,

                     <&slv_lrclk8>,

                     <&slv_lrclk9>;

            clock-names = "pclk",

                          "mst_in0",

                          "mst_in1",

                          "mst_in2",

                          "mst_in3",

                          "mst_in4",

                          "mst_in5",

                          "mst_in6",

                          "mst_in7",

                          "slv_sclk0",

                          "slv_sclk1",

                          "slv_sclk2",

                          "slv_sclk3",

                          "slv_sclk4",

                          "slv_sclk5",

                          "slv_sclk6",

                          "slv_sclk7",

                          "slv_sclk8",

                          "slv_sclk9",

                          "slv_lrclk0",

                          "slv_lrclk1",

                          "slv_lrclk2",

                          "slv_lrclk3",

                          "slv_lrclk4",

                          "slv_lrclk5",

                          "slv_lrclk6",

                          "slv_lrclk7",

                          "slv_lrclk8",

                          "slv_lrclk9";

            resets = <&reset RESET_AUDIO>;

        };

    };

Documentation/devicetree/bindings/clock/amlogic,c3-peripherals-clkc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/amlogic,c3-peripherals-clkc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic C3 series Peripheral Clock Controller



maintainers:

  - Neil Armstrong <neil.armstrong@linaro.org>

  - Jerome Brunet <jbrunet@baylibre.com>

  - Xianwei Zhao <xianwei.zhao@amlogic.com>

  - Chuan Liu <chuan.liu@amlogic.com>



properties:

  compatible:

    const: amlogic,c3-peripherals-clkc



  reg:

    maxItems: 1



  clocks:

    minItems: 16

    items:

      - description: input oscillator (usually at 24MHz)

      - description: input oscillators multiplexer

      - description: input fix pll

      - description: input fclk div 2

      - description: input fclk div 2p5

      - description: input fclk div 3

      - description: input fclk div 4

      - description: input fclk div 5

      - description: input fclk div 7

      - description: input gp0 pll

      - description: input gp1 pll

      - description: input hifi pll

      - description: input sys clk

      - description: input axi clk

      - description: input sys pll div 16

      - description: input cpu clk div 16

      - description: input pad clock for rtc clk (optional)



  clock-names:

    minItems: 16

    items:

      - const: xtal_24m

      - const: oscin

      - const: fix

      - const: fdiv2

      - const: fdiv2p5

      - const: fdiv3

      - const: fdiv4

      - const: fdiv5

      - const: fdiv7

      - const: gp0

      - const: gp1

      - const: hifi

      - const: sysclk

      - const: axiclk

      - const: sysplldiv16

      - const: cpudiv16

      - const: pad_osc



  "#clock-cells":

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - "#clock-cells"



additionalProperties: false



examples:

  - |

    apb {

        #address-cells = <2>;

        #size-cells = <2>;



        clock-controller@0 {

            compatible = "amlogic,c3-peripherals-clkc";

            reg = <0x0 0x0 0x0 0x49c>;

            #clock-cells = <1>;

            clocks = <&xtal_24m>,

                     <&scmi_clk 8>,

                     <&scmi_clk 12>,

                     <&clkc_pll 3>,

                     <&clkc_pll 5>,

                     <&clkc_pll 7>,

                     <&clkc_pll 9>,

                     <&clkc_pll 11>,

                     <&clkc_pll 13>,

                     <&clkc_pll 15>,

                     <&scmi_clk 13>,

                     <&clkc_pll 17>,

                     <&scmi_clk 9>,

                     <&scmi_clk 10>,

                     <&scmi_clk 14>,

                     <&scmi_clk 15>;

            clock-names = "xtal_24m",

                          "oscin",

                          "fix",

                          "fdiv2",

                          "fdiv2p5",

                          "fdiv3",

                          "fdiv4",

                          "fdiv5",

                          "fdiv7",

                          "gp0",

                          "gp1",

                          "hifi",

                          "sysclk",

                          "axiclk",

                          "sysplldiv16",

                          "cpudiv16";

        };

    };