Commit 59854811 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2021-02-04' of... 

Merge tag 'drm-intel-fixes-2021-02-04' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

drm/i915 fixes for v5.11-rc7:
- Skip vswing programming for TBT
- Power up combo PHY lanes for HDMI
- Fix double YUV range correction on HDR planes
- Fix the MST PBN divider calculation
- Fix LTTPR vswing/pre-emp setting in non-transparent mode
- Move the breadcrumb to the signaler if completed upon cancel
- Close race between enable_breadcrumbs and cancel_breadcrumbs
- Drop lru bumping on display unpinning

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87bld0f36b.fsf@intel.com
parents cfd4951f 88ebe1f5

drivers/gpu/drm/drm_dp_mst_topology.c

+18 −6
Original line number Diff line number Diff line
@@ -3629,14 +3629,26 @@ static int drm_dp_send_up_ack_reply(struct drm_dp_mst_topology_mgr *mgr, 
	return 0;

}



static int drm_dp_get_vc_payload_bw(u8 dp_link_bw, u8  dp_link_count)

/**

 * drm_dp_get_vc_payload_bw - get the VC payload BW for an MST link

 * @link_rate: link rate in 10kbits/s units

 * @link_lane_count: lane count

 *

 * Calculate the total bandwidth of a MultiStream Transport link. The returned

 * value is in units of PBNs/(timeslots/1 MTP). This value can be used to

 * convert the number of PBNs required for a given stream to the number of

 * timeslots this stream requires in each MTP.

 */

int drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count)

{

	if (dp_link_bw == 0 || dp_link_count == 0)

		DRM_DEBUG_KMS("invalid link bandwidth in DPCD: %x (link count: %d)\n",

			      dp_link_bw, dp_link_count);

	if (link_rate == 0 || link_lane_count == 0)

		DRM_DEBUG_KMS("invalid link rate/lane count: (%d / %d)\n",

			      link_rate, link_lane_count);



	return dp_link_bw * dp_link_count / 2;

	/* See DP v2.0 2.6.4.2, VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */

	return link_rate * link_lane_count / 54000;

}

EXPORT_SYMBOL(drm_dp_get_vc_payload_bw);



/**

 * drm_dp_read_mst_cap() - check whether or not a sink supports MST
@@ -3692,7 +3704,7 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms 
			goto out_unlock;

		}



		mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr->dpcd[1],

		mgr->pbn_div = drm_dp_get_vc_payload_bw(drm_dp_bw_code_to_link_rate(mgr->dpcd[1]),

							mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK);

		if (mgr->pbn_div == 0) {

			ret = -EINVAL;

drivers/gpu/drm/i915/display/intel_ddi.c

+27 −16
Original line number Diff line number Diff line
@@ -2754,6 +2754,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 
	int n_entries, ln;

	u32 val;



	if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)

		return;



	ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);

	if (level >= n_entries) {

		drm_dbg_kms(&dev_priv->drm,
@@ -2890,6 +2893,9 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 
	u32 val, dpcnt_mask, dpcnt_val;

	int n_entries, ln;



	if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)

		return;



	ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);



	if (level >= n_entries)
@@ -3531,6 +3537,23 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 
	intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));

}



static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,

				     const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);

	enum phy phy = intel_port_to_phy(i915, encoder->port);



	if (intel_phy_is_combo(i915, phy)) {

		bool lane_reversal =

			dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;



		intel_combo_phy_power_up_lanes(i915, phy, false,

					       crtc_state->lane_count,

					       lane_reversal);

	}

}



static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,

				  struct intel_encoder *encoder,

				  const struct intel_crtc_state *crtc_state,
@@ -3620,14 +3643,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 
	 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up

	 * the used lanes of the DDI.

	 */

	if (intel_phy_is_combo(dev_priv, phy)) {

		bool lane_reversal =

			dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;



		intel_combo_phy_power_up_lanes(dev_priv, phy, false,

					       crtc_state->lane_count,

					       lane_reversal);

	}

	intel_ddi_power_up_lanes(encoder, crtc_state);



	/*

	 * 7.g Configure and enable DDI_BUF_CTL
@@ -3712,14 +3728,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 
	else

		intel_prepare_dp_ddi_buffers(encoder, crtc_state);



	if (intel_phy_is_combo(dev_priv, phy)) {

		bool lane_reversal =

			dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;



		intel_combo_phy_power_up_lanes(dev_priv, phy, false,

					       crtc_state->lane_count,

					       lane_reversal);

	}

	intel_ddi_power_up_lanes(encoder, crtc_state);



	intel_ddi_init_dp_buf_reg(encoder, crtc_state);

	if (!is_mst)
@@ -4205,6 +4214,8 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 
		intel_de_write(dev_priv, reg, val);

	}



	intel_ddi_power_up_lanes(encoder, crtc_state);



	/* In HDMI/DVI mode, the port width, and swing/emphasis values

	 * are ignored so nothing special needs to be done besides

	 * enabling the port.

drivers/gpu/drm/i915/display/intel_display.c

+4 −5
Original line number Diff line number Diff line
@@ -2309,7 +2309,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, 
		 */

		ret = i915_vma_pin_fence(vma);

		if (ret != 0 && INTEL_GEN(dev_priv) < 4) {

			i915_gem_object_unpin_from_display_plane(vma);

			i915_vma_unpin(vma);

			vma = ERR_PTR(ret);

			goto err;

		}
@@ -2327,12 +2327,9 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, 








void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)









{









	i915_gem_object_lock(vma->obj, NULL);









	if (flags & PLANE_HAS_FENCE)









		i915_vma_unpin_fence(vma);









	i915_gem_object_unpin_from_display_plane(vma);









	i915_gem_object_unlock(vma->obj);

















	i915_vma_unpin(vma);









	i915_vma_put(vma);









}
















@@ -4807,6 +4804,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,







			plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;









	} else if (fb->format->is_yuv) {









		plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;









		if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)









			plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;









	}

















	return plane_color_ctl;
































drivers/gpu/drm/i915/display/intel_dp.c



+1
−19






























Original line number
Diff line number
Diff line







@@ -4637,24 +4637,6 @@ ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,







	intel_de_posting_read(dev_priv, intel_dp->output_reg);









}



















void intel_dp_set_signal_levels(struct intel_dp *intel_dp,









				const struct intel_crtc_state *crtc_state)









{









	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);









	u8 train_set = intel_dp->train_set[0];



















	drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",









		    train_set & DP_TRAIN_VOLTAGE_SWING_MASK,









		    train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");









	drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",









		    (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>









		    DP_TRAIN_PRE_EMPHASIS_SHIFT,









		    train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?









		    " (max)" : "");



















	intel_dp->set_signal_levels(intel_dp, crtc_state);









}



















void









intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,









				       const struct intel_crtc_state *crtc_state,








@@ -5703,7 +5685,7 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp,

















	intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);



















	intel_dp_set_signal_levels(intel_dp, crtc_state);









	intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);



















	intel_dp_phy_pattern_update(intel_dp, crtc_state);










































drivers/gpu/drm/i915/display/intel_dp.h



+0
−3






























Original line number
Diff line number
Diff line







@@ -96,9 +96,6 @@ void







intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,









				       const struct intel_crtc_state *crtc_state,









				       u8 dp_train_pat);









void









intel_dp_set_signal_levels(struct intel_dp *intel_dp,









			   const struct intel_crtc_state *crtc_state);









void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,









			   u8 *link_bw, u8 *rate_select);









bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);