Commit 5a0b11a1 authored by Vasant Hegde's avatar Vasant Hegde Committed by Joerg Roedel
Browse files

iommu/amd: Remove iommu_v2 module 



AMD GPU driver which was the only in-kernel user of iommu_v2 module
removed dependency on iommu_v2 module.

Also we are working on adding SVA support in AMD IOMMU driver. Device
drivers are expected to use common SVA framework to enable device
PASID/PRI features.

Removing iommu_v2 module and then adding SVA simplifies the development.
Hence remove iommu_v2 module.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarVasant Hegde <vasant.hegde@amd.com>
Reviewed-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Reviewed-by: default avatarJerry Snitselaar <jsnitsel@redhat.com>
Tested-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Link: https://lore.kernel.org/r/20231006095706.5694-2-vasant.hegde@amd.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 7016b300

drivers/iommu/amd/Kconfig

+0 −9
Original line number Diff line number Diff line
@@ -22,15 +22,6 @@ config AMD_IOMMU 
	  your BIOS for an option to enable it or if you have an IVRS ACPI

	  table.



config AMD_IOMMU_V2

	tristate "AMD IOMMU Version 2 driver"

	depends on AMD_IOMMU

	select MMU_NOTIFIER

	help

	  This option enables support for the AMD IOMMUv2 features of the IOMMU

	  hardware. Select this option if you want to use devices that support

	  the PCI PRI and PASID interface.



config AMD_IOMMU_DEBUGFS

	bool "Enable AMD IOMMU internals in DebugFS"

	depends on AMD_IOMMU && IOMMU_DEBUGFS

drivers/iommu/amd/Makefile

+0 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only

obj-$(CONFIG_AMD_IOMMU) += iommu.o init.o quirks.o io_pgtable.o io_pgtable_v2.o

obj-$(CONFIG_AMD_IOMMU_DEBUGFS) += debugfs.o
 
obj-$(CONFIG_AMD_IOMMU_V2) += iommu_v2.o

drivers/iommu/amd/amd_iommu.h

+0 −5
Original line number Diff line number Diff line
@@ -38,9 +38,6 @@ extern int amd_iommu_guest_ir; 
extern enum io_pgtable_fmt amd_iommu_pgtable;

extern int amd_iommu_gpt_level;



/* IOMMUv2 specific functions */

struct iommu_domain;



bool amd_iommu_v2_supported(void);

struct amd_iommu *get_amd_iommu(unsigned int idx);

u8 amd_iommu_pc_get_max_banks(unsigned int idx);
@@ -57,8 +54,6 @@ void amd_iommu_pdev_disable_cap_pri(struct pci_dev *pdev); 


int amd_iommu_register_ppr_notifier(struct notifier_block *nb);

int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb);

void amd_iommu_domain_direct_map(struct iommu_domain *dom);

int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids);

int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid, u64 address);

void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);

void amd_iommu_domain_update(struct protection_domain *domain);

drivers/iommu/amd/iommu.c

+0 −40
Original line number Diff line number Diff line
@@ -2568,46 +2568,6 @@ int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) 
}

EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);



void amd_iommu_domain_direct_map(struct iommu_domain *dom)

{

	struct protection_domain *domain = to_pdomain(dom);

	unsigned long flags;



	spin_lock_irqsave(&domain->lock, flags);



	if (domain->iop.pgtbl_cfg.tlb)

		free_io_pgtable_ops(&domain->iop.iop.ops);



	spin_unlock_irqrestore(&domain->lock, flags);

}

EXPORT_SYMBOL(amd_iommu_domain_direct_map);



int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)

{

	struct protection_domain *pdom = to_pdomain(dom);

	unsigned long flags;

	int ret;



	spin_lock_irqsave(&pdom->lock, flags);



	/*

	 * Save us all sanity checks whether devices already in the

	 * domain support IOMMUv2. Just force that the domain has no

	 * devices attached when it is switched into IOMMUv2 mode.

	 */

	ret = -EBUSY;

	if (pdom->dev_cnt > 0 || pdom->flags & PD_IOMMUV2_MASK)

		goto out;



	if (!pdom->gcr3_tbl)

		ret = setup_gcr3_table(pdom, pasids);



out:

	spin_unlock_irqrestore(&pdom->lock, flags);

	return ret;

}

EXPORT_SYMBOL(amd_iommu_domain_enable_v2);



static int __flush_pasid(struct protection_domain *domain, u32 pasid,

			 u64 address, bool size)

{

drivers/iommu/amd/iommu_v2.c

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