Commit 5a7144d6 authored by Chen Wang's avatar Chen Wang
Browse files

dt-bindings: clock: sophgo: add RP gate clocks for SG2042 



Add bindings for the gate clocks of RP subsystem for Sophgo SG2042.

Signed-off-by: default avatarChen Wang <unicorn_wang@outlook.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
parent 88a26c3c

Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/sophgo,sg2042-rpgate.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Sophgo SG2042 Gate Clock Generator for RP(riscv processors) subsystem



maintainers:

  - Chen Wang <unicorn_wang@outlook.com>



properties:

  compatible:

    const: sophgo,sg2042-rpgate



  reg:

    maxItems: 1



  clocks:

    items:

      - description: Gate clock for RP subsystem



  clock-names:

    items:

      - const: rpgate



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/sophgo,sg2042-rpgate.h> for valid indices.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    clock-controller@20000000 {

      compatible = "sophgo,sg2042-rpgate";

      reg = <0x20000000 0x10000>;

      clocks = <&clkgen 85>;

      clock-names = "rpgate";

      #clock-cells = <1>;

    };

include/dt-bindings/clock/sophgo,sg2042-rpgate.h

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/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */

/*

 * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.

 */



#ifndef __DT_BINDINGS_SOPHGO_SG2042_RPGATE_H__

#define __DT_BINDINGS_SOPHGO_SG2042_RPGATE_H__



#define GATE_CLK_RXU0			0

#define GATE_CLK_RXU1			1

#define GATE_CLK_RXU2			2

#define GATE_CLK_RXU3			3

#define GATE_CLK_RXU4			4

#define GATE_CLK_RXU5			5

#define GATE_CLK_RXU6			6

#define GATE_CLK_RXU7			7

#define GATE_CLK_RXU8			8

#define GATE_CLK_RXU9			9

#define GATE_CLK_RXU10			10

#define GATE_CLK_RXU11			11

#define GATE_CLK_RXU12			12

#define GATE_CLK_RXU13			13

#define GATE_CLK_RXU14			14

#define GATE_CLK_RXU15			15

#define GATE_CLK_RXU16			16

#define GATE_CLK_RXU17			17

#define GATE_CLK_RXU18			18

#define GATE_CLK_RXU19			19

#define GATE_CLK_RXU20			20

#define GATE_CLK_RXU21			21

#define GATE_CLK_RXU22			22

#define GATE_CLK_RXU23			23

#define GATE_CLK_RXU24			24

#define GATE_CLK_RXU25			25

#define GATE_CLK_RXU26			26

#define GATE_CLK_RXU27			27

#define GATE_CLK_RXU28			28

#define GATE_CLK_RXU29			29

#define GATE_CLK_RXU30			30

#define GATE_CLK_RXU31			31

#define GATE_CLK_MP0			32

#define GATE_CLK_MP1			33

#define GATE_CLK_MP2			34

#define GATE_CLK_MP3			35

#define GATE_CLK_MP4			36

#define GATE_CLK_MP5			37

#define GATE_CLK_MP6			38

#define GATE_CLK_MP7			39

#define GATE_CLK_MP8			40

#define GATE_CLK_MP9			41

#define GATE_CLK_MP10			42

#define GATE_CLK_MP11			43

#define GATE_CLK_MP12			44

#define GATE_CLK_MP13			45

#define GATE_CLK_MP14			46

#define GATE_CLK_MP15			47



#endif /* __DT_BINDINGS_SOPHGO_SG2042_RPGATE_H__ */