Commit 5b15b1f1 authored by Jacob Keller's avatar Jacob Keller Committed by Tony Nguyen
Browse files

ice: rename TS_LL_READ* macros to REG_LL_PROXY_H_* 



The TS_LL_READ macros are used as part of the low latency Tx timestamp
interface. A future firmware extension will add support for performing PHY
timer updates over this interface. Using TS_LL_READ as the prefix for these
macros will be confusing once the interface is used for other purposes.

Rename the macros, using the prefix REG_LL_PROXY_H, to better clarify that
this is for the low latency interface.
Additionally add macros for PF_SB_ATQBAH and PF_SB_ATQBAL registers to
better clarify content of this registers as PF_SB_ATQBAH contain low
part of Tx timestamp

Co-developed-by: default avatarKarol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: default avatarKarol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: default avatarJacob Keller <jacob.e.keller@intel.com>
Reviewed-by: default avatarMilena Olech <milena.olech@intel.com>
Signed-off-by: default avatarAnton Nadezhdin <anton.nadezhdin@intel.com>
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
parent 95aca43b

drivers/net/ethernet/intel/ice/ice_ptp.c

+7 −7
Original line number Diff line number Diff line
@@ -490,9 +490,9 @@ void ice_ptp_req_tx_single_tstamp(struct ice_ptp_tx *tx, u8 idx) 
	ice_trace(tx_tstamp_fw_req, tx->tstamps[idx].skb, idx);



	/* Write TS index to read to the PF register so the FW can read it */

	wr32(&pf->hw, PF_SB_ATQBAL,

	     TS_LL_READ_TS_INTR | FIELD_PREP(TS_LL_READ_TS_IDX, idx) |

	     TS_LL_READ_TS);

	wr32(&pf->hw, REG_LL_PROXY_H,

	     REG_LL_PROXY_H_TS_INTR_ENA | FIELD_PREP(REG_LL_PROXY_H_TS_IDX, idx) |

	     REG_LL_PROXY_H_EXEC);

	tx->last_ll_ts_idx_read = idx;

}
@@ -519,20 +519,20 @@ void ice_ptp_complete_tx_single_tstamp(struct ice_ptp_tx *tx) 


	ice_trace(tx_tstamp_fw_done, tx->tstamps[idx].skb, idx);



	val = rd32(&pf->hw, PF_SB_ATQBAL);

	val = rd32(&pf->hw, REG_LL_PROXY_H);



	/* When the bit is cleared, the TS is ready in the register */

	if (val & TS_LL_READ_TS) {

	if (val & REG_LL_PROXY_H_EXEC) {

		dev_err(ice_pf_to_dev(pf), "Failed to get the Tx tstamp - FW not ready");

		return;

	}



	/* High 8 bit value of the TS is on the bits 16:23 */

	raw_tstamp = FIELD_GET(TS_LL_READ_TS_HIGH, val);

	raw_tstamp = FIELD_GET(REG_LL_PROXY_H_TS_HIGH, val);

	raw_tstamp <<= 32;



	/* Read the low 32 bit value */

	raw_tstamp |= (u64)rd32(&pf->hw, PF_SB_ATQBAH);

	raw_tstamp |= (u64)rd32(&pf->hw, REG_LL_PROXY_L);



	/* Devices using this interface always verify the timestamp differs

	 * relative to the last cached timestamp value.

drivers/net/ethernet/intel/ice/ice_ptp_hw.c

+7 −7
Original line number Diff line number Diff line
@@ -4861,24 +4861,24 @@ ice_read_phy_tstamp_ll_e810(struct ice_hw *hw, u8 idx, u8 *hi, u32 *lo) 
	int err;



	/* Write TS index to read to the PF register so the FW can read it */

	val = FIELD_PREP(TS_LL_READ_TS_IDX, idx) | TS_LL_READ_TS;

	wr32(hw, PF_SB_ATQBAL, val);

	val = FIELD_PREP(REG_LL_PROXY_H_TS_IDX, idx) | REG_LL_PROXY_H_EXEC;

	wr32(hw, REG_LL_PROXY_H, val);



	/* Read the register repeatedly until the FW provides us the TS */

	err = read_poll_timeout_atomic(rd32, val,

				       !FIELD_GET(TS_LL_READ_TS, val), 10,

				       TS_LL_READ_TIMEOUT, false, hw,

				       PF_SB_ATQBAL);

				       !FIELD_GET(REG_LL_PROXY_H_EXEC, val), 10,

				       REG_LL_PROXY_H_TIMEOUT_US, false, hw,

				       REG_LL_PROXY_H);

	if (err) {

		ice_debug(hw, ICE_DBG_PTP, "Failed to read PTP timestamp using low latency read\n");

		return err;

	}



	/* High 8 bit value of the TS is on the bits 16:23 */

	*hi = FIELD_GET(TS_LL_READ_TS_HIGH, val);

	*hi = FIELD_GET(REG_LL_PROXY_H_TS_HIGH, val);



	/* Read the low 32 bit value and set the TS valid bit */

	*lo = rd32(hw, PF_SB_ATQBAH) | TS_VALID;

	*lo = rd32(hw, REG_LL_PROXY_L) | TS_VALID;



	return 0;

}

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

+8 −5
Original line number Diff line number Diff line
@@ -689,11 +689,14 @@ static inline bool ice_is_dual(struct ice_hw *hw) 
#define BYTES_PER_IDX_ADDR_L		4



/* Tx timestamp low latency read definitions */

#define TS_LL_READ_TIMEOUT		2000

#define TS_LL_READ_TS_HIGH		GENMASK(23, 16)

#define TS_LL_READ_TS_IDX		GENMASK(29, 24)

#define TS_LL_READ_TS_INTR		BIT(30)

#define TS_LL_READ_TS			BIT(31)

#define REG_LL_PROXY_H_TIMEOUT_US	2000

#define REG_LL_PROXY_H_TS_HIGH		GENMASK(23, 16)

#define REG_LL_PROXY_H_TS_IDX		GENMASK(29, 24)

#define REG_LL_PROXY_H_TS_INTR_ENA	BIT(30)

#define REG_LL_PROXY_H_EXEC		BIT(31)



#define REG_LL_PROXY_L			PF_SB_ATQBAH

#define REG_LL_PROXY_H			PF_SB_ATQBAL



/* Internal PHY timestamp address */

#define TS_L(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U))