Commit 5b179fe0 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-6.11-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 

Pull RISC-V fixes from Palmer Dabbelt:

 - reintroduce the text patching global icache flush

 - fix syscall entry code to correctly initialize a0, which manifested
   as a strace bug

 - XIP kernels now map the entire kernel, which fixes boot under at
   least DEBUG_VIRTUAL=y

 - initialize all nodes in the acpi_early_node_map initializer

 - fix OOB access in the Andes vendor extension probing code

 - A new key for scalar misaligned access performance in hwprobe, which
   correctly treat the values as an enum (as opposed to a bitmap)

* tag 'riscv-for-linus-6.11-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: Fix out-of-bounds when accessing Andes per hart vendor extension array
  RISC-V: hwprobe: Add SCALAR to misaligned perf defines
  RISC-V: hwprobe: Add MISALIGNED_PERF key
  RISC-V: ACPI: NUMA: initialize all values of acpi_early_node_map to NUMA_NO_NODE
  riscv: change XIP's kernel_map.size to be size of the entire kernel
  riscv: entry: always initialize regs->a0 to -ENOSYS
  riscv: Re-introduce global icache flush in patch_text_XXX()
parents 4a621e29 32d5f7ad

Documentation/arch/riscv/hwprobe.rst

+22 −14
Original line number Diff line number Diff line
@@ -239,25 +239,33 @@ The following keys are defined: 
       ratified in commit 98918c844281 ("Merge pull request #1217 from

       riscv/zawrs") of riscv-isa-manual.



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance

  information about the selected set of processors.

* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values to

     :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was

     mistakenly classified as a bitmask rather than a value.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned

    accesses is unknown.

* :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`: An enum value describing

  the performance of misaligned scalar native word accesses on the selected set

  of processors.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are

    emulated via software, either in or below the kernel.  These accesses are

    always extremely slow.

  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of

    misaligned scalar accesses is unknown.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned accesses are slower

    than equivalent byte accesses.  Misaligned accesses may be supported

    directly in hardware, or trapped and emulated by software.

  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned scalar

    accesses are emulated via software, either in or below the kernel.  These

    accesses are always extremely slow.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned accesses are faster

    than equivalent byte accesses.

  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned scalar native

    word sized accesses are slower than the equivalent quantity of byte

    accesses. Misaligned accesses may be supported directly in hardware, or

    trapped and emulated by software.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are

    not supported at all and will generate a misaligned address fault.

  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned scalar native

    word sized accesses are faster than the equivalent quantity of byte

    accesses.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned scalar

    accesses are not supported at all and will generate a misaligned address

    fault.



* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which

  represents the size of the Zicboz block in bytes.

arch/riscv/include/asm/hwprobe.h

+1 −1
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ 


#include <uapi/asm/hwprobe.h>



#define RISCV_HWPROBE_MAX_KEY 8

#define RISCV_HWPROBE_MAX_KEY 9



static inline bool riscv_hwprobe_key_is_valid(__s64 key)

{

arch/riscv/include/uapi/asm/hwprobe.h

+6 −0
Original line number Diff line number Diff line
@@ -82,6 +82,12 @@ struct riscv_hwprobe { 
#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE	6

#define RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS	7

#define RISCV_HWPROBE_KEY_TIME_CSR_FREQ	8

#define RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF	9

#define		RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN		0

#define		RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED	1

#define		RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW		2

#define		RISCV_HWPROBE_MISALIGNED_SCALAR_FAST		3

#define		RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED	4

/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */



/* Flags */

arch/riscv/kernel/acpi_numa.c

+1 −1
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ 


#include <asm/numa.h>



static int acpi_early_node_map[NR_CPUS] __initdata = { NUMA_NO_NODE };

static int acpi_early_node_map[NR_CPUS] __initdata = { [0 ... NR_CPUS - 1] = NUMA_NO_NODE };



int __init acpi_numa_get_nid(unsigned int cpu)

{

arch/riscv/kernel/patch.c

+4 −0
Original line number Diff line number Diff line
@@ -205,6 +205,8 @@ int patch_text_set_nosync(void *addr, u8 c, size_t len) 
	int ret;



	ret = patch_insn_set(addr, c, len);

	if (!ret)

		flush_icache_range((uintptr_t)addr, (uintptr_t)addr + len);



	return ret;

}
@@ -239,6 +241,8 @@ int patch_text_nosync(void *addr, const void *insns, size_t len) 
	int ret;



	ret = patch_insn_write(addr, insns, len);

	if (!ret)

		flush_icache_range((uintptr_t)addr, (uintptr_t)addr + len);



	return ret;

}