Commit 5b1ae9de authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge branch 'for-next/feat_mte_store_only' into for-next/core 

* for-next/feat_mte_store_only:
  : MTE feature to restrict tag checking to store only operations
  kselftest/arm64/mte: Add MTE_STORE_ONLY testcases
  kselftest/arm64/mte: Preparation for mte store only test
  kselftest/arm64/abi: Add MTE_STORE_ONLY feature hwcap test
  KVM: arm64: Expose MTE_STORE_ONLY feature to guest
  arm64/hwcaps: Add MTE_STORE_ONLY hwcaps
  arm64/kernel: Support store-only mte tag check
  prctl: Introduce PR_MTE_STORE_ONLY
  arm64/cpufeature: Add MTE_STORE_ONLY feature
parents 3ae8cef2 1f488fb9

Documentation/arch/arm64/elf_hwcaps.rst

+3 −0
Original line number Diff line number Diff line
@@ -438,6 +438,9 @@ HWCAP2_POE 
HWCAP3_MTE_FAR

    Functionality implied by ID_AA64PFR2_EL1.MTEFAR == 0b0001.



HWCAP3_MTE_STORE_ONLY

    Functionality implied by ID_AA64PFR2_EL1.MTESTOREONLY == 0b0001.



4. Unused AT_HWCAP bits

-----------------------

arch/arm64/include/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -177,6 +177,7 @@ 


#define __khwcap3_feature(x)		(const_ilog2(HWCAP3_ ## x) + 128)

#define KERNEL_HWCAP_MTE_FAR		__khwcap3_feature(MTE_FAR)

#define KERNEL_HWCAP_MTE_STORE_ONLY	__khwcap3_feature(MTE_STORE_ONLY)



/*

 * This yields a mask that user programs can use to figure out what

arch/arm64/include/asm/processor.h

+2 −0
Original line number Diff line number Diff line
@@ -23,6 +23,8 @@ 
#define MTE_CTRL_TCF_ASYNC		(1UL << 17)

#define MTE_CTRL_TCF_ASYMM		(1UL << 18)



#define MTE_CTRL_STORE_ONLY		(1UL << 19)



#ifndef __ASSEMBLY__



#include <linux/build_bug.h>

arch/arm64/include/uapi/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -144,5 +144,6 @@ 
 * HWCAP3 flags - for AT_HWCAP3

 */

#define HWCAP3_MTE_FAR		(1UL << 0)

#define HWCAP3_MTE_STORE_ONLY		(1UL << 1)



#endif /* _UAPI__ASM_HWCAP_H */

arch/arm64/kernel/cpufeature.c

+9 −0
Original line number Diff line number Diff line
@@ -321,6 +321,7 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 
static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = {

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTEFAR_SHIFT, 4, ID_AA64PFR2_EL1_MTEFAR_NI),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT, 4, ID_AA64PFR2_EL1_MTESTOREONLY_NI),

	ARM64_FTR_END,

};
@@ -2914,6 +2915,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.matches = has_cpuid_feature,

		ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTEFAR, IMP)

	},

	{

		.desc = "Store Only MTE Tag Check",

		.capability = ARM64_MTE_STORE_ONLY,

		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.matches = has_cpuid_feature,

		ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTESTOREONLY, IMP)

	},

#endif /* CONFIG_ARM64_MTE */

	{

		.desc = "RCpc load-acquire (LDAPR)",
@@ -3258,6 +3266,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 
	HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE),

	HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3),

	HWCAP_CAP(ID_AA64PFR2_EL1, MTEFAR, IMP, CAP_HWCAP, KERNEL_HWCAP_MTE_FAR),

	HWCAP_CAP(ID_AA64PFR2_EL1, MTESTOREONLY, IMP, CAP_HWCAP , KERNEL_HWCAP_MTE_STORE_ONLY),

#endif /* CONFIG_ARM64_MTE */

	HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV),

	HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP),