Commit 5b289913 authored by Wesley Cheng's avatar Wesley Cheng Committed by Vinod Koul
Browse files

phy: qualcomm: qmp-combo: Update QMP PHY with Glymur settings 



For SuperSpeed USB to work properly, there is a set of HW settings that
need to be programmed into the USB blocks within the QMP PHY.  Ensure that
these settings follow the latest settings mentioned in the HW programming
guide.  The QMP USB PHY on Glymur is a USB43 based PHY that will have some
new ways to define certain registers, such as the replacement of TXA/RXA
and TXB/RXB register sets.  This was replaced with the LALB register set.

There are also some PHY init updates to modify the PCS MISC register space.
Without these, the QMP PHY PLL locking fails.

Signed-off-by: default avatarWesley Cheng <wesley.cheng@oss.qualcomm.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20251209-linux-next-12825-v8-8-42133596bda0@oss.qualcomm.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent c9543cca

drivers/phy/qualcomm/phy-qcom-qmp-combo.c

+285 −0
Original line number Diff line number Diff line
@@ -31,9 +31,11 @@ 


#include "phy-qcom-qmp.h"

#include "phy-qcom-qmp-pcs-aon-v6.h"

#include "phy-qcom-qmp-pcs-aon-v8.h"

#include "phy-qcom-qmp-pcs-misc-v3.h"

#include "phy-qcom-qmp-pcs-misc-v4.h"

#include "phy-qcom-qmp-pcs-misc-v5.h"

#include "phy-qcom-qmp-pcs-misc-v8.h"

#include "phy-qcom-qmp-pcs-usb-v4.h"

#include "phy-qcom-qmp-pcs-usb-v5.h"

#include "phy-qcom-qmp-pcs-usb-v6.h"
@@ -47,6 +49,8 @@ 
#include "phy-qcom-qmp-dp-phy-v5.h"

#include "phy-qcom-qmp-dp-phy-v6.h"



#include "phy-qcom-qmp-usb43-pcs-v8.h"



/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */

/* DP PHY soft reset */

#define SW_DPPHY_RESET				BIT(0)
@@ -98,6 +102,7 @@ enum qphy_reg_layout { 
	QPHY_TX_HIGHZ_DRVR_EN,

	QPHY_TX_TRANSCEIVER_BIAS_EN,



	QPHY_AON_TOGGLE_ENABLE,

	/* Keep last to ensure regs_layout arrays are properly initialized */

	QPHY_LAYOUT_SIZE

};
@@ -260,6 +265,233 @@ static const unsigned int qmp_v8_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_TX_TRANSCEIVER_BIAS_EN]	= QSERDES_V8_TX_TRANSCEIVER_BIAS_EN,

};



static const unsigned int qmp_v8_n3_usb43dpphy_regs_layout[QPHY_LAYOUT_SIZE] = {

	[QPHY_SW_RESET]			= QPHY_V8_USB43_PCS_SW_RESET,

	[QPHY_START_CTRL]			= QPHY_V8_USB43_PCS_START_CONTROL,

	[QPHY_PCS_STATUS]			= QPHY_V8_USB43_PCS_PCS_STATUS1,

	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V8_USB43_PCS_POWER_DOWN_CONTROL,



	/* In PCS_USB */

	[QPHY_PCS_AUTONOMOUS_MODE_CTRL]	= QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL,

	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]	= QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR,



	[QPHY_PCS_CLAMP_ENABLE]			= QPHY_V8_PCS_AON_USB3_AON_CLAMP_ENABLE,

	[QPHY_AON_TOGGLE_ENABLE]		= QPHY_V8_PCS_AON_USB3_AON_TOGGLE_ENABLE,



	[QPHY_COM_RESETSM_CNTRL]		= QSERDES_V8_COM_RESETSM_CNTRL,

	[QPHY_COM_C_READY_STATUS]		= QSERDES_V8_COM_C_READY_STATUS,

	[QPHY_COM_CMN_STATUS]			= QSERDES_V8_COM_CMN_STATUS,

	[QPHY_COM_BIAS_EN_CLKBUFLR_EN]	= QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN,



	[QPHY_TX_TX_DRV_LVL]			= QSERDES_V8_LALB_TX0_DRV_LVL,

	[QPHY_TX_TX_EMP_POST1_LVL]		= QSERDES_V8_LALB_TX0_EMP_POST1_LVL,

	[QPHY_TX_HIGHZ_DRVR_EN]			= QSERDES_V8_LALB_HIGHZ_DRVR_EN,

	[QPHY_TX_TRANSCEIVER_BIAS_EN]	= QSERDES_V8_LALB_TRANSMITTER_EN_CTRL,

};



static const struct qmp_phy_init_tbl glymur_usb43dp_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE1, 0xe1),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE1, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CP_CTRL_MODE1, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE1, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE1, 0x36),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORECLK_DIV_MODE1, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE1, 0x1a),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE1, 0x41),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE1, 0x41),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MSB_MODE1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE1, 0xab),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE1, 0xaa),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE1, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x13),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE1, 0x4d),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE1, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x95),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x4b),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0xe1),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CP_CTRL_MODE0, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE0, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0, 0x36),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORECLK_DIV_MODE0, 0x05),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x1a),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x41),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MSB_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE0, 0xab),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0xaa),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0, 0x4d),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BG_TIMER, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_EN_CENTER, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_PER1, 0x62),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_PER2, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_BUF_ENABLE, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_IVCO, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_IVCO_MODE1, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_EN_SEL, 0x1a),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP_EN, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP_CFG, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_CTRL, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_MAP, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORE_CLK_EN, 0xa0),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_CONFIG_1, 0x76),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SVS_MODE_CLK_SEL, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_SPARE_FOR_ECO, 0x40),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_1, 0x40),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_2, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_3, 0x60),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PSM_CAL_EN, 0x05),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x33),

	QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xaf),

};



static const struct qmp_phy_init_tbl glymur_usb43dp_pcs_misc_tbl[] = {

	QMP_PHY_INIT_CFG(QPHY_V8_PCS_MISC_PCS_MISC_CONFIG1, 0x01),

};



static const struct qmp_phy_init_tbl glymur_usb43dp_pcs_tbl[] = {

	QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG1, 0xc4),

	QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG2, 0x89),

	QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG3, 0x20),

	QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG6, 0x13),

	QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_REFGEN_REQ_CONFIG1, 0x21),

	QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_RX_SIGDET_LVL, 0x55),

	QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),

	QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),

	QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_TSYNC_RSYNC_TIME, 0xa4),

	QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_RX_CONFIG, 0x0a),

	QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_TSYNC_DLY_TIME, 0x04),

	QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_ALIGN_DETECT_CONFIG1, 0xd4),

	QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_ALIGN_DETECT_CONFIG2, 0x30),

	QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_PCS_TX_RX_CONFIG, 0x0c),

	QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_EQ_CONFIG1, 0x4b),

	QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_EQ_CONFIG5, 0x10),

};



static const struct qmp_phy_init_tbl glymur_usb43dp_pcs_usb_tbl[] = {

	QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL, 0xf8),

	QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2, 0x07),

};



static const struct qmp_phy_init_tbl glymur_usb43dp_lalb_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CLKBUF_ENABLE, 0x81),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_LVL_UPDATE_CTRL, 0x0d),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL3, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL4, 0x8D),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TRANSMITTER_EN_CTRL, 0x13),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_1, 0x0c),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_3, 0x11),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_4, 0x11),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_CAL_CTRL, 0x20),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_RESTRIM_CAL_CTRL, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_POST_CAL_OFFSET, 0x10),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_VREF_SEL, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_RESTRIM_VREF_SEL, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_ANA_INTERFACE_SELECT2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCS_INTERFACE_SELECT1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B0, 0xa4),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B1, 0xa2),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B2, 0x6e),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B3, 0x51),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B4, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B5, 0x26),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B6, 0x12),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B7, 0x2a),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B0, 0x4c),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B1, 0xc4),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B2, 0x38),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B3, 0x64),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B4, 0x0c),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B5, 0x4b),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B6, 0x12),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B7, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_DCC_ANA_CTRL2, 0x0c),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT1_RATE1, 0x26),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT2_RATE1, 0x26),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT1_RATE2, 0x26),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT2_RATE2, 0x26),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_INIT_RATE_0_1, 0x11),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_INIT_RATE_2_3, 0x11),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_CODE_OVRD_RATE1, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_CODE_OVRD_RATE2, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF1_RATE1, 0x15),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF2_RATE1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF1_RATE2, 0x22),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF2_RATE2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CODE_OVRD_RATE_2_3, 0x22),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE1, 0xff),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND2_RATE1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE2, 0xff),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND2_RATE2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_LOWER_FREQ_DIFF_BND_RATE1, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_LOWER_FREQ_DIFF_BND_RATE2, 0x09),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_SUMMER_CAL_SPD_MODE_RATE_0123, 0x2f),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_CAL_CODE_OVERRIDE_RATE1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_CAL_CODE_OVERRIDE_RATE2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_CAL_CTRL2, 0x85),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_CAL_CTRL3, 0x45),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_POSTCAL_OFFSET_RATE1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_POSTCAL_OFFSET_RATE2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_ENABLES, 0x0c),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_CNTRL, 0xa3),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_LVL, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_DEGLITCH_CNTRL, 0x0e),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_CAL_CTRL1, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_CAL_CTRL2_AND_CDR_LOCK_EDGE, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_CAL_TRIM, 0x66),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_FREQ_LOCK_DET_DLY_RATE1, 0xff),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_FREQ_LOCK_DET_DLY_RATE2, 0x32),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_CP_CUR_FLL_RATE1, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_CP_CUR_FLL_RATE2, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_CP_CUR_PLL_RATE1, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_CP_CUR_PLL_RATE2, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_CCODE_RATE_01, 0x76),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_CCODE_RATE_23, 0x67),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_FAST_RATE_0_1, 0x20),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_FAST_RATE_2_3, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_FLL_RATE_0_1, 0x33),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_FLL_RATE_2_3, 0x43),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_PLL_RATE_0_1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_PLL_RATE_2_3, 0x51),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_FLL_DIV_RATIO_RATE_0123, 0xe5),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CAP_CODE_RATE_0123, 0xf5),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_TYPE_CONFIG, 0x1f),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_EN_LOWFREQ, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_FUNC_CTRL, 0xd0),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_GM_CAL_EN, 0x1f),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_GM_CAL_RES_RATE0_1, 0x88),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_GM_CAL_RES_RATE2_3, 0x88),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_AUX_CLK_CTRL, 0x20),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_EOM_CTRL1, 0x10),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_EQU_ADAPTOR_CNTRL2, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_EQU_ADAPTOR_CNTRL3, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_EQU_ADAPTOR_CNTRL4, 0xaa),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CTLE_POST_CAL_OFFSET_RATE_0_1_2, 0x77),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_VGA_CAL_CNTRL1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_VGA_CAL_MAN_VAL_RATE0_1, 0xdd),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_VGA_CAL_MAN_VAL_RATE2_3, 0xd8),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_DFE_TAP1_DAC_ENABLE, 0x1c),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_DFE_TAP2_DAC_ENABLE, 0x1c),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_DFE_TAP345_DAC_ENABLE, 0x18),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_DFE_TAP67_DAC_ENABLE, 0x10),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_IQTUNE_CTRL, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_IQTUNE_MAN_INDEX, 0x10),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_IQTUNE_DIV2_CTRL_RATE0123, 0x1C),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CAP_CODE_OVRD_MUXES, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V8_LALB_DIG_BKUP_CTRL16, 0x37),

};



static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
@@ -1663,6 +1895,12 @@ static struct regulator_bulk_data qmp_phy_vreg_l[] = { 
	{ .supply = "vdda-pll", .init_load_uA = 36000, },

};



static struct regulator_bulk_data qmp_phy_vreg_refgen[] = {

	{ .supply = "vdda-phy", .init_load_uA = 21800 },

	{ .supply = "vdda-pll", .init_load_uA = 36000 },

	{ .supply = "refgen", .init_load_uA = 3270 },

};



static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {

	{ 0x00, 0x0c, 0x15, 0x1a },

	{ 0x02, 0x0e, 0x16, 0xff },
@@ -1807,6 +2045,8 @@ struct qmp_phy_cfg { 
	int pcs_tbl_num;

	const struct qmp_phy_init_tbl *pcs_usb_tbl;

	int pcs_usb_tbl_num;

	const struct qmp_phy_init_tbl *pcs_misc_tbl;

	int pcs_misc_tbl_num;



	const struct qmp_phy_init_tbl *dp_serdes_tbl;

	int dp_serdes_tbl_num;
@@ -2000,6 +2240,19 @@ static const struct qmp_combo_offsets qmp_combo_offsets_v8 = { 
	.dp_dp_phy	= 0x3c00,

};



static const struct qmp_combo_offsets qmp_combo_usb43dp_offsets_v8 = {

	.com		= 0x0000,

	.usb3_pcs_aon	= 0x0100,

	.usb3_serdes	= 0x1000,

	.usb3_pcs_misc	= 0x1400,

	.usb3_pcs	= 0x1600,

	.usb3_pcs_usb	= 0x1900,

	.dp_serdes	= 0x2000,

	.dp_dp_phy	= 0x2400,

	.txa		= 0x4000,

	.txb		= 0x5000,

};



static const struct qmp_phy_cfg sar2130p_usb3dpphy_cfg = {

	.offsets		= &qmp_combo_offsets_v3,
@@ -2544,6 +2797,27 @@ static const struct qmp_phy_cfg sm8750_usb3dpphy_cfg = { 
	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),

};



static const struct qmp_phy_cfg glymur_usb3dpphy_cfg = {

	.offsets		= &qmp_combo_usb43dp_offsets_v8,



	.serdes_tbl		= glymur_usb43dp_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(glymur_usb43dp_serdes_tbl),

	.tx_tbl			= glymur_usb43dp_lalb_tbl,

	.tx_tbl_num		= ARRAY_SIZE(glymur_usb43dp_lalb_tbl),

	.pcs_tbl		= glymur_usb43dp_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(glymur_usb43dp_pcs_tbl),

	.pcs_usb_tbl		= glymur_usb43dp_pcs_usb_tbl,

	.pcs_usb_tbl_num	= ARRAY_SIZE(glymur_usb43dp_pcs_usb_tbl),

	.pcs_misc_tbl		= glymur_usb43dp_pcs_misc_tbl,

	.pcs_misc_tbl_num	= ARRAY_SIZE(glymur_usb43dp_pcs_misc_tbl),



	.regs			= qmp_v8_n3_usb43dpphy_regs_layout,

	.reset_list		= msm8996_usb3phy_reset_l,

	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),

	.vreg_list		= qmp_phy_vreg_refgen,

	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_refgen),

};



static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp)

{

	const struct qmp_phy_cfg *cfg = qmp->cfg;
@@ -3040,6 +3314,7 @@ static int qmp_combo_com_init(struct qmp_combo *qmp, bool force) 
{

	const struct qmp_phy_cfg *cfg = qmp->cfg;

	void __iomem *com = qmp->com;

	void __iomem *pcs_aon = qmp->pcs_aon;

	int ret;

	u32 val;
@@ -3075,6 +3350,10 @@ static int qmp_combo_com_init(struct qmp_combo *qmp, bool force) 
			SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |

			SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);



	/* override hardware control for reset of qmp phy */

	if (pcs_aon && cfg->regs[QPHY_AON_TOGGLE_ENABLE])

		qphy_clrbits(pcs_aon, cfg->regs[QPHY_AON_TOGGLE_ENABLE], 0x1);



	/* Use software based port select and switch on typec orientation */

	val = SW_PORTSELECT_MUX;

	if (qmp->orientation == TYPEC_ORIENTATION_REVERSE)
@@ -3252,6 +3531,8 @@ static int qmp_combo_usb_power_on(struct phy *phy) 
	qmp_configure_lane(qmp->dev, rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);



	qmp_configure(qmp->dev, pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);

	qmp_configure(qmp->dev, qmp->pcs_misc, cfg->pcs_misc_tbl, cfg->pcs_misc_tbl_num);





	if (pcs_usb)

		qmp_configure(qmp->dev, pcs_usb, cfg->pcs_usb_tbl,
@@ -4347,6 +4628,10 @@ static int qmp_combo_probe(struct platform_device *pdev) 
}



static const struct of_device_id qmp_combo_of_match_table[] = {

	{

		.compatible = "qcom,glymur-qmp-usb3-dp-phy",

		.data = &glymur_usb3dpphy_cfg,

	},

	{

		.compatible = "qcom,sar2130p-qmp-usb3-dp-phy",

		.data = &sar2130p_usb3dpphy_cfg,

drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v8.h

0 → 100644
+17 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.

 */



#ifndef QCOM_PHY_QMP_PCS_AON_V8_H_

#define QCOM_PHY_QMP_PCS_AON_V8_H_



/* Only for QMP V8 PHY - PCS_AON registers */

#define QPHY_V8_PCS_AON_USB3_AON_CLAMP_ENABLE     0x00

#define QPHY_V8_PCS_AON_USB4_AON_CLAMP_ENABLE     0x04

#define QPHY_V8_PCS_AON_USB3_AON_TOGGLE_ENABLE    0x08

#define QPHY_V8_PCS_AON_USB4_AON_TOGGLE_ENABLE    0x0c

#define QPHY_V8_PCS_AON_DP_AON_TOGGLE_ENABLE      0x10

#define QPHY_V8_PCS_AON_DUMMY_STATUS              0x14



#endif

drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v8.h

0 → 100644
+12 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.

 */



#ifndef QCOM_PHY_QMP_PCS_MISC_V8_H_

#define QCOM_PHY_QMP_PCS_MISC_V8_H_



/* Only for QMP V8 PHY - PCS_MISC registers */

#define QPHY_V8_PCS_MISC_PCS_MISC_CONFIG1		0x08



#endif

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-lalb-v8.h

0 → 100644
+639 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/phy/qualcomm/phy-qcom-qmp-usb43-pcs-v8.h

0 → 100644
+33 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.

 */



#ifndef QCOM_PHY_QMP_USB43_PCS_V8_H_

#define QCOM_PHY_QMP_USB43_PCS_V8_H_



#define QPHY_V8_USB43_PCS_SW_RESET				0x000

#define QPHY_V8_USB43_PCS_PCS_STATUS1				0x014

#define QPHY_V8_USB43_PCS_POWER_DOWN_CONTROL			0x040

#define QPHY_V8_USB43_PCS_START_CONTROL				0x044

#define QPHY_V8_USB43_PCS_POWER_STATE_CONFIG1			0x090

#define QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG1			0x0c4

#define QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG2			0x0c8

#define QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG3			0x0cc

#define QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG6			0x0d8

#define QPHY_V8_USB43_PCS_REFGEN_REQ_CONFIG1			0x0dc

#define QPHY_V8_USB43_PCS_RX_SIGDET_LVL				0x188

#define QPHY_V8_USB43_PCS_RCVR_DTCT_DLY_P1U2_L			0x190

#define QPHY_V8_USB43_PCS_RCVR_DTCT_DLY_P1U2_H			0x194

#define QPHY_V8_USB43_PCS_RATE_SLEW_CNTRL1			0x198

#define QPHY_V8_USB43_PCS_TSYNC_RSYNC_TIME			0x1ac

#define QPHY_V8_USB43_PCS_RX_CONFIG				0x1b0

#define QPHY_V8_USB43_PCS_TSYNC_DLY_TIME			0x1b4

#define QPHY_V8_USB43_PCS_ALIGN_DETECT_CONFIG1			0x1c0

#define QPHY_V8_USB43_PCS_ALIGN_DETECT_CONFIG2			0x1c4

#define QPHY_V8_USB43_PCS_PCS_TX_RX_CONFIG			0x1d0

#define QPHY_V8_USB43_PCS_EQ_CONFIG1				0x1dc

#define QPHY_V8_USB43_PCS_EQ_CONFIG2				0x1e0

#define QPHY_V8_USB43_PCS_EQ_CONFIG5				0x1ec



#endif