Merge tag 'drm-misc-next-2026-03-05' of...

            properties:

              data-lanes:

                description: array of physical DSI data lane indexes.

                minItems: 1

                items:

                  - const: 1

                  - const: 2

                  - const: 3

                  - const: 4

            required:

              - data-lanes

module_param_named(force_snoop, ivpu_force_snoop, bool, 0444);

MODULE_PARM_DESC(force_snoop, "Force snooping for NPU host memory access");

static struct ivpu_user_limits *ivpu_user_limits_alloc(struct ivpu_device *vdev, uid_t uid)

{

	struct ivpu_user_limits *limits;

	limits = kzalloc_obj(*limits);

	if (!limits)

		return ERR_PTR(-ENOMEM);

	kref_init(&limits->ref);

	atomic_set(&limits->db_count, 0);

	limits->vdev = vdev;

	limits->uid = uid;

	/* Allow root user to allocate all contexts */

	if (uid == 0) {

		limits->max_ctx_count = ivpu_get_context_count(vdev);

		limits->max_db_count = ivpu_get_doorbell_count(vdev);

	} else {

		limits->max_ctx_count = ivpu_get_context_count(vdev) / 2;

		limits->max_db_count = ivpu_get_doorbell_count(vdev) / 2;

	}

	hash_add(vdev->user_limits, &limits->hash_node, uid);

	return limits;

}

static struct ivpu_user_limits *ivpu_user_limits_get(struct ivpu_device *vdev)

{

	struct ivpu_user_limits *limits;

	uid_t uid = current_uid().val;

	guard(mutex)(&vdev->user_limits_lock);

	hash_for_each_possible(vdev->user_limits, limits, hash_node, uid) {

		if (limits->uid == uid) {

			if (kref_read(&limits->ref) >= limits->max_ctx_count) {

				ivpu_dbg(vdev, IOCTL, "User %u exceeded max ctx count %u\n", uid,

					 limits->max_ctx_count);

				return ERR_PTR(-EMFILE);

			}

			kref_get(&limits->ref);

			return limits;

		}

	}

	return ivpu_user_limits_alloc(vdev, uid);

}

static void ivpu_user_limits_release(struct kref *ref)

{

	struct ivpu_user_limits *limits = container_of(ref, struct ivpu_user_limits, ref);

	struct ivpu_device *vdev = limits->vdev;

	lockdep_assert_held(&vdev->user_limits_lock);

	drm_WARN_ON(&vdev->drm, atomic_read(&limits->db_count));

	hash_del(&limits->hash_node);

	kfree(limits);

}

static void ivpu_user_limits_put(struct ivpu_device *vdev, struct ivpu_user_limits *limits)

{

	guard(mutex)(&vdev->user_limits_lock);

	kref_put(&limits->ref, ivpu_user_limits_release);

}

struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv)

{

	struct ivpu_device *vdev = file_priv->vdev;

	mutex_unlock(&vdev->context_list_lock);

	pm_runtime_put_autosuspend(vdev->drm.dev);

	ivpu_user_limits_put(vdev, file_priv->user_limits);

	mutex_destroy(&file_priv->ms_lock);

	mutex_destroy(&file_priv->lock);

	kfree(file_priv);

		args->value = ivpu_hw_dpu_max_freq_get(vdev);

		break;

	case DRM_IVPU_PARAM_NUM_CONTEXTS:

		args->value = ivpu_get_context_count(vdev);

		args->value = file_priv->user_limits->max_ctx_count;

		break;

	case DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS:

		args->value = vdev->hw->ranges.user.start;

{

	struct ivpu_device *vdev = to_ivpu_device(dev);

	struct ivpu_file_priv *file_priv;

	struct ivpu_user_limits *limits;

	u32 ctx_id;

	int idx, ret;

	if (!drm_dev_enter(dev, &idx))

		return -ENODEV;

	limits = ivpu_user_limits_get(vdev);

	if (IS_ERR(limits)) {

		ret = PTR_ERR(limits);

		goto err_dev_exit;

	}

	file_priv = kzalloc_obj(*file_priv);

	if (!file_priv) {

		ret = -ENOMEM;

		goto err_dev_exit;

		goto err_user_limits_put;

	}

	INIT_LIST_HEAD(&file_priv->ms_instance_list);

	file_priv->vdev = vdev;

	file_priv->bound = true;

	file_priv->user_limits = limits;

	kref_init(&file_priv->ref);

	mutex_init(&file_priv->lock);

	mutex_init(&file_priv->ms_lock);

	mutex_destroy(&file_priv->ms_lock);

	mutex_destroy(&file_priv->lock);

	kfree(file_priv);

err_user_limits_put:

	ivpu_user_limits_put(vdev, limits);

err_dev_exit:

	drm_dev_exit(idx);

	return ret;

	ivpu_ipc_consumer_del(vdev, &cons);

	if (!ret && ipc_hdr.data_addr != IVPU_IPC_BOOT_MSG_DATA_ADDR) {

		ivpu_err(vdev, "Invalid NPU ready message: 0x%x\n",

			 ipc_hdr.data_addr);

		ivpu_err(vdev, "Invalid NPU ready message: 0x%x\n", ipc_hdr.data_addr);

		return -EIO;

	}

	xa_init_flags(&vdev->submitted_jobs_xa, XA_FLAGS_ALLOC1);

	xa_init_flags(&vdev->db_xa, XA_FLAGS_ALLOC1);

	INIT_LIST_HEAD(&vdev->bo_list);

	hash_init(vdev->user_limits);

	vdev->db_limit.min = IVPU_MIN_DB;

	vdev->db_limit.max = IVPU_MAX_DB;

	if (ret)

		goto err_xa_destroy;

	ret = drmm_mutex_init(&vdev->drm, &vdev->user_limits_lock);

	if (ret)

		goto err_xa_destroy;

	ret = drmm_mutex_init(&vdev->drm, &vdev->submitted_jobs_lock);

	if (ret)

		goto err_xa_destroy;

#include <drm/drm_mm.h>

#include <drm/drm_print.h>

#include <linux/hashtable.h>

#include <linux/pci.h>

#include <linux/xarray.h>

#include <uapi/drm/ivpu_accel.h>

/* SSID 1 is used by the VPU to represent reserved context */

#define IVPU_RESERVED_CONTEXT_MMU_SSID 1

#define IVPU_USER_CONTEXT_MIN_SSID     2

#define IVPU_USER_CONTEXT_MAX_SSID     (IVPU_USER_CONTEXT_MIN_SSID + 63)

#define IVPU_USER_CONTEXT_MAX_SSID     (IVPU_USER_CONTEXT_MIN_SSID + 128)

#define IVPU_MIN_DB 1

#define IVPU_MAX_DB 255

#define IVPU_JOB_ID_JOB_MASK		GENMASK(7, 0)

#define IVPU_JOB_ID_CONTEXT_MASK	GENMASK(31, 8)

#define IVPU_NUM_PRIORITIES    4

#define IVPU_NUM_CMDQS_PER_CTX (IVPU_NUM_PRIORITIES)

#define IVPU_CMDQ_MIN_ID 1

#define IVPU_CMDQ_MAX_ID 255

struct ivpu_ipc_info;

struct ivpu_pm_info;

struct ivpu_user_limits {

	struct hlist_node hash_node;

	struct ivpu_device *vdev;

	struct kref ref;

	u32 max_ctx_count;

	u32 max_db_count;

	u32 uid;

	atomic_t db_count;

};

struct ivpu_device {

	struct drm_device drm;

	void __iomem *regb;

	struct mutex context_list_lock; /* Protects user context addition/removal */

	struct xarray context_xa;

	struct xa_limit context_xa_limit;

	DECLARE_HASHTABLE(user_limits, 8);

	struct mutex user_limits_lock; /* Protects user_limits */

	struct xarray db_xa;

	struct xa_limit db_limit;

	struct list_head ms_instance_list;

	struct ivpu_bo *ms_info_bo;

	struct xa_limit job_limit;

	struct ivpu_user_limits *user_limits;

	u32 job_id_next;

	struct xa_limit cmdq_limit;

	u32 cmdq_id_next;

	return (ctx_limit.max - ctx_limit.min + 1);

}

static inline u32 ivpu_get_doorbell_count(struct ivpu_device *vdev)

{

	struct xa_limit db_limit = vdev->db_limit;

	return (db_limit.max - db_limit.min + 1);

}

static inline u32 ivpu_get_platform(struct ivpu_device *vdev)

{

	WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);

	ret = xa_alloc_cyclic(&file_priv->cmdq_xa, &cmdq->id, cmdq, file_priv->cmdq_limit,

			      &file_priv->cmdq_id_next, GFP_KERNEL);

	if (ret < 0) {

		ivpu_err(vdev, "Failed to allocate command queue ID: %d\n", ret);

		ivpu_dbg(vdev, IOCTL, "Failed to allocate command queue ID: %d\n", ret);

		goto err_free_cmdq;

	}

static int ivpu_register_db(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq)

{

	struct ivpu_user_limits *limits = file_priv->user_limits;

	struct ivpu_device *vdev = file_priv->vdev;

	int ret;

	if (atomic_inc_return(&limits->db_count) > limits->max_db_count) {

		ivpu_dbg(vdev, IOCTL, "Maximum number of %u doorbells for uid %u reached\n",

			 limits->max_db_count, limits->uid);

		ret = -EBUSY;

		goto err_dec_db_count;

	}

	ret = xa_alloc_cyclic(&vdev->db_xa, &cmdq->db_id, NULL, vdev->db_limit, &vdev->db_next,

			      GFP_KERNEL);

	if (ret < 0) {

		ivpu_err(vdev, "Failed to allocate doorbell ID: %d\n", ret);

		return ret;

		ivpu_dbg(vdev, IOCTL, "Failed to allocate doorbell ID: %d\n", ret);

		goto err_dec_db_count;

	}

	if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW)

	else

		ret = ivpu_jsm_register_db(vdev, file_priv->ctx.id, cmdq->db_id,

					   cmdq->mem->vpu_addr, ivpu_bo_size(cmdq->mem));

	if (!ret) {

		ivpu_dbg(vdev, JOB, "DB %d registered to cmdq %d ctx %d priority %d\n",

			 cmdq->db_id, cmdq->id, file_priv->ctx.id, cmdq->priority);

	} else {

	if (ret) {

		xa_erase(&vdev->db_xa, cmdq->db_id);

		cmdq->db_id = 0;

		goto err_dec_db_count;

	}

	ivpu_dbg(vdev, JOB, "DB %d registered to cmdq %d ctx %d priority %d\n",

		 cmdq->db_id, cmdq->id, file_priv->ctx.id, cmdq->priority);

	return 0;

err_dec_db_count:

	atomic_dec(&limits->db_count);

	return ret;

}

	}

	xa_erase(&file_priv->vdev->db_xa, cmdq->db_id);

	atomic_dec(&file_priv->user_limits->db_count);

	cmdq->db_id = 0;

	return 0;

static void ivpu_cmdq_destroy(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq)

{

	lockdep_assert_held(&file_priv->lock);

	ivpu_cmdq_unregister(file_priv, cmdq);

	xa_erase(&file_priv->cmdq_xa, cmdq->id);

	ivpu_cmdq_free(file_priv, cmdq);

	mutex_lock(&file_priv->lock);

	xa_for_each(&file_priv->cmdq_xa, cmdq_id, cmdq) {

		if (cmdq->db_id) {

			xa_erase(&file_priv->vdev->db_xa, cmdq->db_id);

			atomic_dec(&file_priv->user_limits->db_count);

			cmdq->db_id = 0;

		}

	}

	mutex_unlock(&file_priv->lock);

}

/* SPDX-License-Identifier: MIT */

/*

 * Copyright (c) 2020-2024, Intel Corporation.

 * Copyright (c) 2020-2025, Intel Corporation.

 */

/**

 * @addtogroup Boot

 * @{

 */

/**

 * @file

 * @brief Boot API public header file.

 */

#ifndef VPU_BOOT_API_H

#define VPU_BOOT_API_H

/*

/**

 *  The below values will be used to construct the version info this way:

 *  fw_bin_header->api_version[VPU_BOOT_API_VER_ID] = (VPU_BOOT_API_VER_MAJOR << 16) |

 *  VPU_BOOT_API_VER_MINOR;

 *  partial info a build error will be generated.

 */

/*

/**

 * Major version changes that break backward compatibility.

 * Major version must start from 1 and can only be incremented.

 */

#define VPU_BOOT_API_VER_MAJOR 3

/*

/**

 * Minor version changes when API backward compatibility is preserved.

 * Resets to 0 if Major version is incremented.

 */

#define VPU_BOOT_API_VER_MINOR 28

#define VPU_BOOT_API_VER_MINOR 29

/*

/**

 * API header changed (field names, documentation, formatting) but API itself has not been changed

 */

#define VPU_BOOT_API_VER_PATCH 3

#define VPU_BOOT_API_VER_PATCH 4

/*

/**

 * Index in the API version table

 * Must be unique for each API

 */

#pragma pack(push, 4)

/*

/**

 * Firmware image header format

 */

#define VPU_FW_HEADER_SIZE    4096

	u32 firmware_version_size;

	u64 boot_params_load_address;

	u32 api_version[VPU_FW_API_VER_NUM];

	/* Size of memory require for firmware execution */

	/** Size of memory require for firmware execution */

	u32 runtime_size;

	u32 shave_nn_fw_size;

	/*

	/**

	 * Size of primary preemption buffer, assuming a 2-job submission queue.

	 * NOTE: host driver is expected to adapt size accordingly to actual

	 * submission queue size and device capabilities.

	 */

	u32 preemption_buffer_1_size;

	/*

	/**

	 * Size of secondary preemption buffer, assuming a 2-job submission queue.

	 * NOTE: host driver is expected to adapt size accordingly to actual

	 * submission queue size and device capabilities.

	 */

	u32 preemption_buffer_2_size;

	/*

	/**

	 * Maximum preemption buffer size that the FW can use: no need for the host

	 * driver to allocate more space than that specified by these fields.

	 * A value of 0 means no declared limit.

	 */

	u32 preemption_buffer_1_max_size;

	u32 preemption_buffer_2_max_size;

	/* Space reserved for future preemption-related fields. */

	/** Space reserved for future preemption-related fields. */

	u32 preemption_reserved[4];

	/* FW image read only section start address, 4KB aligned */

	/** FW image read only section start address, 4KB aligned */

	u64 ro_section_start_address;

	/* FW image read only section size, 4KB aligned */

	/** FW image read only section size, 4KB aligned */

	u32 ro_section_size;

	u32 reserved;

};

/*

/**

 * Firmware boot parameters format

 */

#define VPU_BOOT_PLL_COUNT     3

#define VPU_BOOT_PLL_OUT_COUNT 4

/** Values for boot_type field */

#define VPU_BOOT_TYPE_COLDBOOT 0

#define VPU_BOOT_TYPE_WARMBOOT 1

#define VPU_TRACE_PROC_BIT_ACT_SHV_3 22

#define VPU_TRACE_PROC_NO_OF_HW_DEVS 23

/* VPU 30xx HW component IDs are sequential, so define first and last IDs. */

/** VPU 30xx HW component IDs are sequential, so define first and last IDs. */

#define VPU_TRACE_PROC_BIT_30XX_FIRST VPU_TRACE_PROC_BIT_LRT

#define VPU_TRACE_PROC_BIT_30XX_LAST  VPU_TRACE_PROC_BIT_SHV_15

	u8 cfg;

};

struct vpu_warm_boot_section {

	u32 src;

	u32 dst;

	u32 size;

	u32 core_id;

	u32 is_clear_op;

};

/*

/**

 * When HW scheduling mode is enabled, a present period is defined.

 * It will be used by VPU to swap between normal and focus priorities

 * to prevent starving of normal priority band (when implemented).

 * Enum for dvfs_mode boot param.

 */

enum vpu_governor {

	VPU_GOV_DEFAULT = 0, /* Default Governor for the system */

	VPU_GOV_MAX_PERFORMANCE = 1, /* Maximum performance governor */

	VPU_GOV_ON_DEMAND = 2, /* On Demand frequency control governor */

	VPU_GOV_POWER_SAVE = 3, /* Power save governor */

	VPU_GOV_ON_DEMAND_PRIORITY_AWARE = 4 /* On Demand priority based governor */

	VPU_GOV_DEFAULT = 0, /** Default Governor for the system */

	VPU_GOV_MAX_PERFORMANCE = 1, /** Maximum performance governor */

	VPU_GOV_ON_DEMAND = 2, /** On Demand frequency control governor */

	VPU_GOV_POWER_SAVE = 3, /** Power save governor */

	VPU_GOV_ON_DEMAND_PRIORITY_AWARE = 4 /** On Demand priority based governor */

};

struct vpu_boot_params {

	u32 magic;

	u32 vpu_id;

	u32 vpu_count;

	u32 pad0[5];

	/* Clock frequencies: 0x20 - 0xFF */

	u32 reserved_0[5];

	/** Clock frequencies: 0x20 - 0xFF */

	u32 frequency;

	u32 pll[VPU_BOOT_PLL_COUNT][VPU_BOOT_PLL_OUT_COUNT];

	u32 reserved_1[12];

	u32 perf_clk_frequency;

	u32 pad1[42];

	/* Memory regions: 0x100 - 0x1FF */

	u32 reserved_2[42];

	/** Memory regions: 0x100 - 0x1FF */

	u64 ipc_header_area_start;

	u32 ipc_header_area_size;

	u64 shared_region_base;

	u32 global_aliased_pio_size;

	u32 autoconfig;

	struct vpu_boot_l2_cache_config cache_defaults[VPU_BOOT_L2_CACHE_CFG_NUM];

	u64 global_memory_allocator_base;

	u32 global_memory_allocator_size;

	u32 reserved_3[3];

	/**

	 * ShaveNN FW section VPU base address

	 * On VPU2.7 HW this address must be within 2GB range starting from L2C_PAGE_TABLE base

	 */

	u64 shave_nn_fw_base;

	u64 save_restore_ret_address; /* stores the address of FW's restore entry point */

	u32 pad2[43];

	/* IRQ re-direct numbers: 0x200 - 0x2FF */

	u64 save_restore_ret_address; /** stores the address of FW's restore entry point */

	u32 reserved_4[43];

	/** IRQ re-direct numbers: 0x200 - 0x2FF */

	s32 watchdog_irq_mss;

	s32 watchdog_irq_nce;

	/* ARM -> VPU doorbell interrupt. ARM is notifying VPU of async command or compute job. */

	/** ARM -> VPU doorbell interrupt. ARM is notifying VPU of async command or compute job. */

	u32 host_to_vpu_irq;

	/* VPU -> ARM job done interrupt. VPU is notifying ARM of compute job completion. */

	/** VPU -> ARM job done interrupt. VPU is notifying ARM of compute job completion. */

	u32 job_done_irq;

	/* VPU -> ARM IRQ line to use to request MMU update. */

	u32 mmu_update_request_irq;

	/* ARM -> VPU IRQ line to use to notify of MMU update completion. */

	u32 mmu_update_done_irq;

	/* ARM -> VPU IRQ line to use to request power level change. */

	u32 set_power_level_irq;

	/* VPU -> ARM IRQ line to use to notify of power level change completion. */

	u32 set_power_level_done_irq;

	/* VPU -> ARM IRQ line to use to notify of VPU idle state change */

	u32 set_vpu_idle_update_irq;

	/* VPU -> ARM IRQ line to use to request counter reset. */

	u32 metric_query_event_irq;

	/* ARM -> VPU IRQ line to use to notify of counter reset completion. */

	u32 metric_query_event_done_irq;

	/* VPU -> ARM IRQ line to use to notify of preemption completion. */

	u32 preemption_done_irq;

	/* Padding. */

	u32 pad3[52];

	/* Silicon information: 0x300 - 0x3FF */

	/** Padding. */

	u32 reserved_5[60];

	/** Silicon information: 0x300 - 0x3FF */

	u32 host_version_id;

	u32 si_stepping;

	u64 device_id;

	u32 crit_tracing_buff_size;

	u64 verbose_tracing_buff_addr;

	u32 verbose_tracing_buff_size;

	u64 verbose_tracing_sw_component_mask; /* TO BE REMOVED */

	u64 verbose_tracing_sw_component_mask; /** TO BE REMOVED */

	/**

	 * Mask of destinations to which logging messages are delivered; bitwise OR

	 * of values defined in vpu_trace_destination enum.

	/** Mask of trace message formats supported by the driver */

	u64 tracing_buff_message_format_mask;

	u64 trace_reserved_1[2];

	/**

	 * Period at which the VPU reads the temp sensor values into MMIO, on

	 * platforms where that is necessary (in ms). 0 to disable reads.

	 */

	u32 temp_sensor_period_ms;

	u32 reserved_6;

	/** PLL ratio for efficient clock frequency */

	u32 pn_freq_pll_ratio;

	/**

	 *       1: IPC message required to save state on D0i3 entry flow.

	 */

	u32 d0i3_delayed_entry;

	/* Time spent by VPU in D0i3 state */

	/** Time spent by VPU in D0i3 state */

	u64 d0i3_residency_time_us;

	/* Value of VPU perf counter at the time of entering D0i3 state . */

	/** Value of VPU perf counter at the time of entering D0i3 state . */

	u64 d0i3_entry_vpu_ts;

	/*

	/**

	 * The system time of the host operating system in microseconds.

	 * E.g the number of microseconds since 1st of January 1970, or whatever

	 * date the host operating system uses to maintain system time.

	 * The KMD is required to update this value on every VPU reset.

	 */

	u64 system_time_us;

	u32 pad4[2];

	/*

	u32 reserved_7[2];

	/**

	 * The delta between device monotonic time and the current value of the

	 * HW timestamp register, in ticks. Written by the firmware during boot.

	 * Can be used by the KMD to calculate device time.

	 */

	u64 device_time_delta_ticks;

	u32 pad7[14];

	/* Warm boot information: 0x400 - 0x43F */

	u32 warm_boot_sections_count;

	u32 warm_boot_start_address_reference;

	u32 warm_boot_section_info_address_offset;

	u32 pad5[13];

	/* Power States transitions timestamps: 0x440 - 0x46F*/

	struct {

		/* VPU_IDLE -> VPU_ACTIVE transition initiated timestamp */

	u32 reserved_8[30];

	/** Power States transitions timestamps: 0x440 - 0x46F*/

	struct power_states_timestamps {

		/** VPU_IDLE -> VPU_ACTIVE transition initiated timestamp */

		u64 vpu_active_state_requested;

		/* VPU_IDLE -> VPU_ACTIVE transition completed timestamp */

		/** VPU_IDLE -> VPU_ACTIVE transition completed timestamp */

		u64 vpu_active_state_achieved;

		/* VPU_ACTIVE -> VPU_IDLE transition initiated timestamp */

		/** VPU_ACTIVE -> VPU_IDLE transition initiated timestamp */

		u64 vpu_idle_state_requested;

		/* VPU_ACTIVE -> VPU_IDLE transition completed timestamp */

		/** VPU_ACTIVE -> VPU_IDLE transition completed timestamp */

		u64 vpu_idle_state_achieved;

		/* VPU_IDLE -> VPU_STANDBY transition initiated timestamp */

		/** VPU_IDLE -> VPU_STANDBY transition initiated timestamp */

		u64 vpu_standby_state_requested;

		/* VPU_IDLE -> VPU_STANDBY transition completed timestamp */

		/** VPU_IDLE -> VPU_STANDBY transition completed timestamp */

		u64 vpu_standby_state_achieved;

	} power_states_timestamps;

	/* VPU scheduling mode. Values defined by VPU_SCHEDULING_MODE_* macros. */

	/** VPU scheduling mode. Values defined by VPU_SCHEDULING_MODE_* macros. */

	u32 vpu_scheduling_mode;

	/* Present call period in milliseconds. */

	/** Present call period in milliseconds. */

	u32 vpu_focus_present_timer_ms;

	/* VPU ECC Signaling */

	/** VPU ECC Signaling */

	u32 vpu_uses_ecc_mca_signal;

	/* Values defined by POWER_PROFILE* macros */

	/** Values defined by POWER_PROFILE* macros */

	u32 power_profile;

	/* Microsecond value for DCT active cycle */

	/** Microsecond value for DCT active cycle */

	u32 dct_active_us;

	/* Microsecond value for DCT inactive cycle */

	/** Microsecond value for DCT inactive cycle */

	u32 dct_inactive_us;

	/* Unused/reserved: 0x488 - 0xFFF */

	u32 pad6[734];

	/** Unused/reserved: 0x488 - 0xFFF */

	u32 reserved_9[734];

};

/* Magic numbers set between host and vpu to detect corruption of tracing init */

/** Magic numbers set between host and vpu to detect corruption of tracing init */

#define VPU_TRACING_BUFFER_CANARY (0xCAFECAFE)

/* Tracing buffer message format definitions */

/** Tracing buffer message format definitions */

#define VPU_TRACING_FORMAT_STRING 0

#define VPU_TRACING_FORMAT_MIPI	  2

/*

/**

 * Header of the tracing buffer.

 * The below defined header will be stored at the beginning of

 * each allocated tracing buffer, followed by a series of 256b

	 * @see VPU_TRACING_BUFFER_CANARY

	 */

	u32 host_canary_start;

	/* offset from start of buffer for trace entries */

	/** offset from start of buffer for trace entries */

	u32 read_index;

	/* keeps track of wrapping on the reader side */

	/** keeps track of wrapping on the reader side */

	u32 read_wrap_count;

	u32 pad_to_cache_line_size_0[13];