Commit 60e9f776 authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm/registers: Generate _HI/LO builders for reg64 



The upstream mesa copy of the GPU regs has shifted more things to reg64
instead of seperate 32b HI/LO reg32's.  This works better with the "new-
style" c++ builders that mesa has been migrating to for a6xx+ (to better
handle register shuffling between gens), but it leaves the C builders
with missing _HI/LO builders.

So handle the special case of reg64, automatically generating the
missing _HI/LO builders.

Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673559/
parent 29e087f3

drivers/gpu/drm/msm/registers/gen_header.py

+7 −0
Original line number Diff line number Diff line
@@ -161,6 +161,7 @@ class Bitset(object): 
	def __init__(self, name, template):

		self.name = name

		self.inline = False

		self.reg = None

		if template:

			self.fields = template.fields[:]

		else:
@@ -266,6 +267,11 @@ class Bitset(object): 
	def dump(self, is_deprecated, prefix=None):

		if prefix is None:

			prefix = self.name

		if self.reg and self.reg.bit_size == 64:

			print("static inline uint32_t %s_LO(uint32_t val)\n{" % prefix)

			print("\treturn val;\n}")

			print("static inline uint32_t %s_HI(uint32_t val)\n{" % prefix)

			print("\treturn val;\n}")

		for f in self.fields:

			if f.name:

				name = prefix + "_" + f.name
@@ -645,6 +651,7 @@ class Parser(object): 


		self.current_reg = Reg(attrs, self.prefix(variant), self.current_array, bit_size)

		self.current_reg.bitset = self.current_bitset

		self.current_bitset.reg = self.current_reg



		if len(self.stack) == 1:

			self.file.append(self.current_reg)