Commit 6191b25d authored by Marc Zyngier's avatar Marc Zyngier Committed by Will Deacon
Browse files

arm64: Unconditionally enable LSE support 



LSE atomics have been in the architecture since ARMv8.1 (released in
2014), and are hopefully supported by all modern toolchains.

Drop the optional nature of LSE support in the kernel, and always
compile the support in, as this really is very little code. LL/SC
still is the default, and the switch to LSE is done dynamically.

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent e3baa5d4

arch/arm64/Kconfig

+0 −16
Original line number Diff line number Diff line
@@ -1873,22 +1873,6 @@ config ARM64_PAN 
	  The feature is detected at runtime, and will remain as a 'nop'

	  instruction if the cpu does not implement the feature.



config ARM64_LSE_ATOMICS

	bool

	default ARM64_USE_LSE_ATOMICS



config ARM64_USE_LSE_ATOMICS

	bool "Atomic instructions"

	default y

	help

	  As part of the Large System Extensions, ARMv8.1 introduces new

	  atomic instructions that are designed specifically to scale in

	  very large systems.



	  Say Y here to make use of these instructions for the in-kernel

	  atomic routines. This incurs a small overhead on CPUs that do

	  not support these instructions.



endmenu # "ARMv8.1 architectural features"



menu "ARMv8.2 architectural features"

arch/arm64/include/asm/insn.h

+0 −23
Original line number Diff line number Diff line
@@ -671,7 +671,6 @@ u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant, 
			  enum aarch64_insn_register Rn,

			  enum aarch64_insn_register Rd,

			  u8 lsb);

#ifdef CONFIG_ARM64_LSE_ATOMICS

u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,

				  enum aarch64_insn_register address,

				  enum aarch64_insn_register value,
@@ -683,28 +682,6 @@ u32 aarch64_insn_gen_cas(enum aarch64_insn_register result, 
			 enum aarch64_insn_register value,

			 enum aarch64_insn_size_type size,

			 enum aarch64_insn_mem_order_type order);

#else

static inline

u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,

				  enum aarch64_insn_register address,

				  enum aarch64_insn_register value,

				  enum aarch64_insn_size_type size,

				  enum aarch64_insn_mem_atomic_op op,

				  enum aarch64_insn_mem_order_type order)

{

	return AARCH64_BREAK_FAULT;

}



static inline

u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,

			 enum aarch64_insn_register address,

			 enum aarch64_insn_register value,

			 enum aarch64_insn_size_type size,

			 enum aarch64_insn_mem_order_type order)

{

	return AARCH64_BREAK_FAULT;

}

#endif

u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type);

u32 aarch64_insn_gen_dsb(enum aarch64_insn_mb_type type);

u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result,

arch/arm64/include/asm/lse.h

+0 −9
Original line number Diff line number Diff line
@@ -4,8 +4,6 @@ 


#include <asm/atomic_ll_sc.h>



#ifdef CONFIG_ARM64_LSE_ATOMICS



#define __LSE_PREAMBLE	".arch_extension lse\n"



#include <linux/compiler_types.h>
@@ -27,11 +25,4 @@ 
#define ARM64_LSE_ATOMIC_INSN(llsc, lse)				\

	ALTERNATIVE(llsc, __LSE_PREAMBLE lse, ARM64_HAS_LSE_ATOMICS)



#else	/* CONFIG_ARM64_LSE_ATOMICS */



#define __lse_ll_sc_body(op, ...)		__ll_sc_##op(__VA_ARGS__)



#define ARM64_LSE_ATOMIC_INSN(llsc, lse)	llsc



#endif	/* CONFIG_ARM64_LSE_ATOMICS */

#endif	/* __ASM_LSE_H */

arch/arm64/kernel/cpufeature.c

+0 −2
Original line number Diff line number Diff line
@@ -2560,7 +2560,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3)

	},

#endif /* CONFIG_ARM64_EPAN */

#ifdef CONFIG_ARM64_LSE_ATOMICS

	{

		.desc = "LSE atomic instructions",

		.capability = ARM64_HAS_LSE_ATOMICS,
@@ -2568,7 +2567,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.matches = has_cpuid_feature,

		ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP)

	},

#endif /* CONFIG_ARM64_LSE_ATOMICS */

	{

		.desc = "Virtualization Host Extensions",

		.capability = ARM64_HAS_VIRT_HOST_EXTN,

arch/arm64/kvm/at.c

+0 −7
Original line number Diff line number Diff line
@@ -1700,7 +1700,6 @@ int __kvm_find_s1_desc_level(struct kvm_vcpu *vcpu, u64 va, u64 ipa, int *level) 
	}

}



#ifdef CONFIG_ARM64_LSE_ATOMICS

static int __lse_swap_desc(u64 __user *ptep, u64 old, u64 new)

{

	u64 tmp = old;
@@ -1725,12 +1724,6 @@ static int __lse_swap_desc(u64 __user *ptep, u64 old, u64 new) 


	return ret;

}

#else

static int __lse_swap_desc(u64 __user *ptep, u64 old, u64 new)

{

	return -EINVAL;

}

#endif



static int __llsc_swap_desc(u64 __user *ptep, u64 old, u64 new)

{