Unverified Commit 63e9bb0d authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'newsoc/andes' into soc/newsoc 

Patches from Ben Zong-You Xie <ben717@andestech.com>:

The Voyager is a 9.6” x 9.6” Micro ATX form factor development board
including Andes QiLai SoC. This patch series adds minimal device tree
files for the QiLai SoC and the Voyager board [1].

Now only support basic uart drivers to boot up into a basic console. Other
features will be added later.

[1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
[2] https://lore.kernel.org/all/20250602060747.689824-1-ben717@andestech.com/

* newsoc/andes:
  MAINTAINERS: Add entry for Andes SoC
  riscv: defconfig: enable Andes SoC
  riscv: dts: andes: add Voyager board device tree
  riscv: dts: andes: add QiLai SoC device tree
  dt-bindings: timer: add Andes machine timer
  dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller
  dt-bindings: interrupt-controller: add Andes QiLai PLIC
  dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings
  riscv: add Andes SoC family Kconfig support
parents 9cf8d2b8 bf40c1a5

Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Andes machine-level software interrupt controller



description:

  In the Andes platform such as QiLai SoC, the PLIC module is instantiated a

  second time with all interrupt sources tied to zero as the software interrupt

  controller (PLIC_SW). PLIC_SW directly connects to the machine-mode

  inter-processor interrupt lines of CPUs, so RISC-V per-CPU local interrupt

  controller is the parent interrupt controller for PLIC_SW. PLIC_SW can

  generate machine-mode inter-processor interrupts through programming its

  registers.



maintainers:

  - Ben Zong-You Xie <ben717@andestech.com>



properties:

  compatible:

    items:

      - enum:

          - andestech,qilai-plicsw

      - const: andestech,plicsw



  reg:

    maxItems: 1



  interrupts-extended:

    minItems: 1

    maxItems: 15872

    description:

      Specifies which harts are connected to the PLIC_SW. Each item must points

      to a riscv,cpu-intc node, which has a riscv cpu node as parent.



additionalProperties: false



required:

  - compatible

  - reg

  - interrupts-extended



examples:

  - |

    interrupt-controller@400000 {

      compatible = "andestech,qilai-plicsw", "andestech,plicsw";

      reg = <0x400000 0x400000>;

      interrupts-extended = <&cpu0intc 3>,

                            <&cpu1intc 3>,

                            <&cpu2intc 3>,

                            <&cpu3intc 3>;

    };

Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

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@@ -53,6 +53,7 @@ properties: 
    oneOf:

      - items:

          - enum:

              - andestech,qilai-plic

              - renesas,r9a07g043-plic

          - const: andestech,nceplic100

      - items:

Documentation/devicetree/bindings/riscv/andes.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/riscv/andes.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Andes SoC-based boards



maintainers:

  - Ben Zong-You Xie <ben717@andestech.com>



description:

  Andes SoC-based boards



properties:

  $nodename:

    const: '/'

  compatible:

    oneOf:

      - items:

          - enum:

              - andestech,voyager

          - const: andestech,qilai



additionalProperties: true

Documentation/devicetree/bindings/timer/andestech,plmt0.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/timer/andestech,plmt0.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Andes machine-level timer



description:

  The Andes machine-level timer device (PLMT0) provides machine-level timer

  functionality for a set of HARTs on a RISC-V platform. It has a single

  fixed-frequency monotonic time counter (MTIME) register and a time compare

  register (MTIMECMP) for each HART connected to the PLMT0. A timer interrupt is

  generated if MTIME >= MTIMECMP.



maintainers:

  - Ben Zong-You Xie <ben717@andestech.com>



properties:

  compatible:

    items:

      - enum:

          - andestech,qilai-plmt

      - const: andestech,plmt0



  reg:

    maxItems: 1



  interrupts-extended:

    minItems: 1

    maxItems: 32

    description:

      Specifies which harts are connected to the PLMT0. Each item must points

      to a riscv,cpu-intc node, which has a riscv cpu node as parent. The

      PLMT0 supports 1 hart up to 32 harts.



additionalProperties: false



required:

  - compatible

  - reg

  - interrupts-extended



examples:

  - |

    interrupt-controller@100000 {

      compatible = "andestech,qilai-plmt", "andestech,plmt0";

      reg = <0x100000 0x100000>;

      interrupts-extended = <&cpu0intc 7>,

                            <&cpu1intc 7>,

                            <&cpu2intc 7>,

                            <&cpu3intc 7>;

    };

MAINTAINERS

+9 −0
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@@ -21293,6 +21293,15 @@ F: drivers/irqchip/irq-riscv-intc.c 
F:	include/linux/irqchip/riscv-aplic.h

F:	include/linux/irqchip/riscv-imsic.h









RISC-V ANDES SoC Support









M:	Ben Zong-You Xie <ben717@andestech.com>









S:	Maintained









T:	git: https://github.com/ben717-linux/linux









F:	Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml









F:	Documentation/devicetree/bindings/riscv/andes.yaml









F:	Documentation/devicetree/bindings/timer/andestech,plmt0.yaml









F:	arch/riscv/boot/dts/andes/

















RISC-V ARCHITECTURE









M:	Paul Walmsley <paul.walmsley@sifive.com>









M:	Palmer Dabbelt <palmer@dabbelt.com>