Commit 63feb35c authored by Aurabindo Pillai's avatar Aurabindo Pillai Committed by Alex Deucher
Browse files

drm/amd/display: temp w/a for DP Link Layer compliance 



[Why&How]
Disabling P-State support on full updates for DCN401 results in
introducing additional communication with SMU. A UCLK hard min message
to SMU takes 4 seconds to go through, which was due to DCN not allowing
pstate switch, which was caused by incorrect value for TTU watermark
before blanking the HUBP prior to DPG on for servicing the test request.

Fix the issue temporarily by disallowing pstate changes for compliance
test while test request handler is reworked for a proper fix.

Fixes: 67ea53a4 ("drm/amd/display: Disable DCN401 UCLK P-State support on full updates")
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarWayne Lin <wayne.lin@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 8a79f7cd)
Cc: stable@vger.kernel.org
parent 23d16ede

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

+13 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ 


#include "dm_helpers.h"

#include "ddc_service_types.h"

#include "clk_mgr.h"



static u32 edid_extract_panel_id(struct edid *edid)

{
@@ -1121,6 +1122,8 @@ bool dm_helpers_dp_handle_test_pattern_request( 
	struct pipe_ctx *pipe_ctx = NULL;

	struct amdgpu_dm_connector *aconnector = link->priv;

	struct drm_device *dev = aconnector->base.dev;

	struct dc_state *dc_state = ctx->dc->current_state;

	struct clk_mgr *clk_mgr = ctx->dc->clk_mgr;

	int i;



	for (i = 0; i < MAX_PIPES; i++) {
@@ -1221,6 +1224,16 @@ bool dm_helpers_dp_handle_test_pattern_request( 
	pipe_ctx->stream->test_pattern.type = test_pattern;

	pipe_ctx->stream->test_pattern.color_space = test_pattern_color_space;



	/* Temp W/A for compliance test failure */

	dc_state->bw_ctx.bw.dcn.clk.p_state_change_support = false;

	dc_state->bw_ctx.bw.dcn.clk.dramclk_khz = clk_mgr->dc_mode_softmax_enabled ?

		clk_mgr->bw_params->dc_mode_softmax_memclk : clk_mgr->bw_params->max_memclk_mhz;

	dc_state->bw_ctx.bw.dcn.clk.idle_dramclk_khz = dc_state->bw_ctx.bw.dcn.clk.dramclk_khz;

	ctx->dc->clk_mgr->funcs->update_clocks(

			ctx->dc->clk_mgr,

			dc_state,

			false);



	dc_link_dp_set_test_pattern(

		(struct dc_link *) link,

		test_pattern,