Commit 64553c79 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Simplify combo PLL frac w/a 



We are applying the combo PLL frac w/a to all TGL+ platforms, except
RKL. I *think* all RKL machines use a 24 MHz refclk (certainly all
machines in our CI do) and so technically never need the adjustment.
But let's assume the hardware is exactly the same anyway and simplify
the code by applying the w/a to all TGL+ platforms.

v2: Keep the 38.4 MHz check

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250402171720.9350-1-ville.syrjala@linux.intel.com


Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
parent efaa1177

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

+2 −5
Original line number Diff line number Diff line
@@ -2604,10 +2604,7 @@ ehl_combo_pll_div_frac_wa_needed(struct intel_display *display) 
{

	return ((display->platform.elkhartlake &&

		 IS_DISPLAY_STEP(display, STEP_B0, STEP_FOREVER)) ||

		 display->platform.dg1 ||

		 display->platform.tigerlake ||

		 display->platform.alderlake_s ||

		 display->platform.alderlake_p) &&

		DISPLAY_VER(display) >= 12) &&

		display->dpll.ref_clks.nssc == 38400;

}