Commit 65599f65 authored by Mitul Golani's avatar Mitul Golani Committed by Ankit Nautiyal
Browse files

drm/i915/scaler: Limit pipe scaler downscaling factors for YUV420 



Limit downscaling to less than 1.5 (source/destination) in
the horizontal direction and 1.0 in the vertical direction,
When configured for Pipe YUV 420 encoding for port output.

Bspec: 50441, 7490, 69901
Signed-off-by: default avatarMitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250120172209.188488-6-mitulkumar.ajitkumar.golani@intel.com
parent 9217f9aa

drivers/gpu/drm/i915/display/skl_scaler.c

+10 −0
Original line number Diff line number Diff line
@@ -459,6 +459,16 @@ static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state, 
		calculate_max_scale(crtc, 0, *scaler_id,

				    &max_hscale, &max_vscale);



		/*

		 * When configured for Pipe YUV 420 encoding for port output,

		 * limit downscaling to less than 1.5 (source/destination) in

		 * the horizontal direction and 1.0 in the vertical direction.

		 */

		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {

			max_hscale = 0x18000 - 1;

			max_vscale = 0x10000;

		}



		hscale = drm_rect_calc_hscale(&src, &crtc_state->pch_pfit.dst,

					      0, max_hscale);

		vscale = drm_rect_calc_vscale(&src, &crtc_state->pch_pfit.dst,