Commit 655c8f51 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Martin K. Petersen
Browse files

scsi: ufs: qcom: dt-bindings: Split SC7180 and similar 



The binding for Qualcomm SoC UFS controllers grew and it will grow
further.  Split SC7180 and several other devices which:

 1. Do not reference ICE as I/O address space, but as a phandle,

 2. Have same order of clocks (SC7180 has one clock less than SC7280 and
    other variants in split binding).

The split allows easier review and maintenance of the binding.

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250731-dt-bindings-ufs-qcom-v2-2-53bb634bf95a@linaro.org


Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 7f224967

Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml

0 → 100644
+167 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/ufs/qcom,sc7180-ufshc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm SC7180 and Other SoCs UFS Controllers



maintainers:

  - Bjorn Andersson <bjorn.andersson@linaro.org>



# Select only our matches, not all jedec,ufs-2.0

select:

  properties:

    compatible:

      contains:

        enum:

          - qcom,msm8998-ufshc

          - qcom,qcs8300-ufshc

          - qcom,sa8775p-ufshc

          - qcom,sc7180-ufshc

          - qcom,sc7280-ufshc

          - qcom,sc8180x-ufshc

          - qcom,sc8280xp-ufshc

          - qcom,sm8250-ufshc

          - qcom,sm8350-ufshc

          - qcom,sm8450-ufshc

          - qcom,sm8550-ufshc

  required:

    - compatible



properties:

  compatible:

    items:

      - enum:

          - qcom,msm8998-ufshc

          - qcom,qcs8300-ufshc

          - qcom,sa8775p-ufshc

          - qcom,sc7180-ufshc

          - qcom,sc7280-ufshc

          - qcom,sc8180x-ufshc

          - qcom,sc8280xp-ufshc

          - qcom,sm8250-ufshc

          - qcom,sm8350-ufshc

          - qcom,sm8450-ufshc

          - qcom,sm8550-ufshc

      - const: qcom,ufshc

      - const: jedec,ufs-2.0



  reg:

    maxItems: 1



  reg-names:

    items:

      - const: std



  clocks:

    minItems: 7

    maxItems: 8



  clock-names:

    minItems: 7

    items:

      - const: core_clk

      - const: bus_aggr_clk

      - const: iface_clk

      - const: core_clk_unipro

      - const: ref_clk

      - const: tx_lane0_sync_clk

      - const: rx_lane0_sync_clk

      - const: rx_lane1_sync_clk



  qcom,ice:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: phandle to the Inline Crypto Engine node



required:

  - compatible

  - reg



allOf:

  - $ref: qcom,ufs-common.yaml



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sc7180-ufshc

    then:

      properties:

        clocks:

          maxItems: 7

        clock-names:

          maxItems: 7

    else:

      properties:

        clocks:

          minItems: 8

        clock-names:

          minItems: 8



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-sm8450.h>

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/gpio/gpio.h>

    #include <dt-bindings/interconnect/qcom,sm8450.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        ufs@1d84000 {

            compatible = "qcom,sm8450-ufshc", "qcom,ufshc",

                         "jedec,ufs-2.0";

            reg = <0x0 0x01d84000 0x0 0x3000>;

            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;

            phys = <&ufs_mem_phy_lanes>;

            phy-names = "ufsphy";

            lanes-per-direction = <2>;

            #reset-cells = <1>;

            resets = <&gcc GCC_UFS_PHY_BCR>;

            reset-names = "rst";

            reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;



            vcc-supply = <&vreg_l7b_2p5>;

            vcc-max-microamp = <1100000>;

            vccq-supply = <&vreg_l9b_1p2>;

            vccq-max-microamp = <1200000>;



            power-domains = <&gcc UFS_PHY_GDSC>;

            iommus = <&apps_smmu 0xe0 0x0>;

            interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,

                            <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;

            interconnect-names = "ufs-ddr", "cpu-ufs";



            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,

                     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

                     <&gcc GCC_UFS_PHY_AHB_CLK>,

                     <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

                     <&rpmhcc RPMH_CXO_CLK>,

                     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

                     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;

            clock-names = "core_clk",

                          "bus_aggr_clk",

                          "iface_clk",

                          "core_clk_unipro",

                          "ref_clk",

                          "tx_lane0_sync_clk",

                          "rx_lane0_sync_clk",

                          "rx_lane1_sync_clk";

            freq-table-hz = <75000000 300000000>,

                            <0 0>,

                            <0 0>,

                            <75000000 300000000>,

                            <75000000 300000000>,

                            <0 0>,

                            <0 0>,

                            <0 0>;

            qcom,ice = <&ice>;

        };

    };

Documentation/devicetree/bindings/ufs/qcom,ufs.yaml

+35 −69
Original line number Diff line number Diff line
@@ -15,7 +15,17 @@ select: 
  properties:

    compatible:

      contains:

        const: qcom,ufshc

        enum:

          - qcom,msm8994-ufshc

          - qcom,msm8996-ufshc

          - qcom,qcs615-ufshc

          - qcom,sdm845-ufshc

          - qcom,sm6115-ufshc

          - qcom,sm6125-ufshc

          - qcom,sm6350-ufshc

          - qcom,sm8150-ufshc

          - qcom,sm8650-ufshc

          - qcom,sm8750-ufshc

  required:

    - compatible
@@ -25,23 +35,12 @@ properties: 
      - enum:

          - qcom,msm8994-ufshc

          - qcom,msm8996-ufshc

          - qcom,msm8998-ufshc

          - qcom,qcs615-ufshc

          - qcom,qcs8300-ufshc

          - qcom,sa8775p-ufshc

          - qcom,sc7180-ufshc

          - qcom,sc7280-ufshc

          - qcom,sc8180x-ufshc

          - qcom,sc8280xp-ufshc

          - qcom,sdm845-ufshc

          - qcom,sm6115-ufshc

          - qcom,sm6125-ufshc

          - qcom,sm6350-ufshc

          - qcom,sm8150-ufshc

          - qcom,sm8250-ufshc

          - qcom,sm8350-ufshc

          - qcom,sm8450-ufshc

          - qcom,sm8550-ufshc

          - qcom,sm8650-ufshc

          - qcom,sm8750-ufshc

      - const: qcom,ufshc
@@ -72,41 +71,6 @@ allOf: 
        compatible:

          contains:

            enum:

              - qcom,sc7180-ufshc

    then:

      properties:

        clocks:

          minItems: 7

          maxItems: 7

        clock-names:

          items:

            - const: core_clk

            - const: bus_aggr_clk

            - const: iface_clk

            - const: core_clk_unipro

            - const: ref_clk

            - const: tx_lane0_sync_clk

            - const: rx_lane0_sync_clk

        reg:

          maxItems: 1

        reg-names:

          maxItems: 1



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,msm8998-ufshc

              - qcom,qcs8300-ufshc

              - qcom,sa8775p-ufshc

              - qcom,sc7280-ufshc

              - qcom,sc8180x-ufshc

              - qcom,sc8280xp-ufshc

              - qcom,sm8250-ufshc

              - qcom,sm8350-ufshc

              - qcom,sm8450-ufshc

              - qcom,sm8550-ufshc

              - qcom,sm8650-ufshc

              - qcom,sm8750-ufshc

    then:
@@ -246,10 +210,10 @@ unevaluatedProperties: false 


examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-sm8450.h>

    #include <dt-bindings/clock/qcom,gcc-sm8150.h>

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/gpio/gpio.h>

    #include <dt-bindings/interconnect/qcom,sm8450.h>

    #include <dt-bindings/interconnect/qcom,sm8150.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    soc {
@@ -257,9 +221,12 @@ examples: 
        #size-cells = <2>;



        ufs@1d84000 {

            compatible = "qcom,sm8450-ufshc", "qcom,ufshc",

            compatible = "qcom,sm8150-ufshc", "qcom,ufshc",

                         "jedec,ufs-2.0";

            reg = <0 0x01d84000 0 0x3000>;

            reg = <0x0 0x01d84000 0x0 0x2500>,

                  <0x0 0x01d90000 0x0 0x8000>;

            reg-names = "std", "ice";



            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;

            phys = <&ufs_mem_phy_lanes>;

            phy-names = "ufsphy";
@@ -275,19 +242,8 @@ examples: 
            vccq-max-microamp = <1200000>;



            power-domains = <&gcc UFS_PHY_GDSC>;

            iommus = <&apps_smmu 0xe0 0x0>;

            interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,

                            <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;

            interconnect-names = "ufs-ddr", "cpu-ufs";

            iommus = <&apps_smmu 0x300 0>;



            clock-names = "core_clk",

                          "bus_aggr_clk",

                          "iface_clk",

                          "core_clk_unipro",

                          "ref_clk",

                          "tx_lane0_sync_clk",

                          "rx_lane0_sync_clk",

                          "rx_lane1_sync_clk";

            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,

                     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

                     <&gcc GCC_UFS_PHY_AHB_CLK>,
@@ -295,15 +251,25 @@ examples: 
                     <&rpmhcc RPMH_CXO_CLK>,

                     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

                     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;

            freq-table-hz = <75000000 300000000>,

                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,

                     <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;

            clock-names = "core_clk",

                          "bus_aggr_clk",

                          "iface_clk",

                          "core_clk_unipro",

                          "ref_clk",

                          "tx_lane0_sync_clk",

                          "rx_lane0_sync_clk",

                          "rx_lane1_sync_clk",

                          "ice_core_clk";

            freq-table-hz = <37500000 300000000>,

                            <0 0>,

                            <0 0>,

                            <37500000 300000000>,

                            <0 0>,

                            <0 0>,

                            <75000000 300000000>,

                            <75000000 300000000>,

                            <0 0>,

                            <0 0>,

                            <0 0>;

            qcom,ice = <&ice>;

                            <0 300000000>;

        };

    };