Commit 67167297 authored by Ley Foon Tan's avatar Ley Foon Tan Committed by Jakub Kicinski
Browse files

net: stmmac: dwmac4: Receive Watchdog Timeout is not in abnormal interrupt summary 



The Receive Watchdog Timeout (RWT, bit[9]) is not part of Abnormal
Interrupt Summary (AIS). Move the RWT handling out of the AIS
condition statement.

From databook, the AIS is the logical OR of the following interrupt bits:

- Bit 1: Transmit Process Stopped
- Bit 7: Receive Buffer Unavailable
- Bit 8: Receive Process Stopped
- Bit 10: Early Transmit Interrupt
- Bit 12: Fatal Bus Error
- Bit 13: Context Descriptor Error

Signed-off-by: default avatarLey Foon Tan <leyfoon.tan@starfivetech.com>
Reviewed-by: default avatarSimon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20241107063637.2122726-4-leyfoon.tan@starfivetech.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 3fccba8f

drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c

+4 −2
Original line number Diff line number Diff line
@@ -185,8 +185,6 @@ int dwmac4_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, 
			x->rx_buf_unav_irq++;

		if (unlikely(intr_status & DMA_CHAN_STATUS_RPS))

			x->rx_process_stopped_irq++;

		if (unlikely(intr_status & DMA_CHAN_STATUS_RWT))

			x->rx_watchdog_irq++;

		if (unlikely(intr_status & DMA_CHAN_STATUS_ETI))

			x->tx_early_irq++;

		if (unlikely(intr_status & DMA_CHAN_STATUS_TPS)) {
@@ -198,6 +196,10 @@ int dwmac4_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, 
			ret = tx_hard_error;

		}

	}



	if (unlikely(intr_status & DMA_CHAN_STATUS_RWT))

		x->rx_watchdog_irq++;



	/* TX/RX NORMAL interrupts */

	if (likely(intr_status & DMA_CHAN_STATUS_RI)) {

		u64_stats_update_begin(&stats->syncp);