Unverified Commit 699646e6 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-fixes', 'clk-renesas', 'clk-rpi', 'clk-eswin' and 'clk-mediatek' into clk-next 

 - ESWIN eic700 SoC clk support
 - Econet EN751221 SoC clock/reset support

* clk-fixes:
  clk: spacemit: ccu_mix: fix inverted condition in ccu_mix_trigger_fc()
  clk: microchip: mpfs-ccc: fix out of bounds access during output registration
  clk: qcom: dispcc-sm8450: use RCG2 ops for DPTX1 AUX clock source

* clk-renesas:
  clk: renesas: Add support for RZ/G3L SoC
  dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3L SoC
  clk: renesas: rzg2l: Re-enable critical module clocks during resume
  clk: renesas: rzg2l: Add rzg2l_mod_clock_init_mstop_helper()
  clk: renesas: rzg2l: Add helper for mod clock enable/disable
  clk: renesas: r9a0{7g04[34],8g045}: Add critical reset entries
  clk: renesas: rzg2l: Add support for critical resets
  clk: renesas: r9a09g056: Remove entries for WDT{0,2,3}
  clk: renesas: r9a06g032: Enable watchdog reset sources
  clk: renesas: cpg-mssr: Use struct_size() helper
  clk: renesas: r9a09g047: Add PCIe clocks and reset
  clk: renesas: r9a09g057: Add PCIe clocks and reset
  clk: renesas: r9a09g056: Add PCIe clocks and reset
  clk: renesas: r9a09g047: Add entries for the RSPIs
  clk: renesas: r9a09g056: Add clock and reset entries for RTC
  clk: renesas: r9a09g057: Remove entries for WDT{0,2,3}
  clk: renesas: r9a09g056: Fix ordering of module clocks array
  clk: renesas: r9a09g057: Fix ordering of module clocks array

* clk-rpi:
  clk: bcm: rpi: Manage clock rate in prepare/unprepare callbacks

* clk-eswin:
  MAINTAINERS: Add entry for ESWIN EIC7700 clock driver
  clk: eswin: Add eic7700 clock driver
  clk: divider: Add devm_clk_hw_register_divider_parent_data
  dt-bindings: clock: eswin: Documentation for eic7700 SoC

* clk-mediatek:
  clk: airoha: Add econet EN751221 clock/reset support to en7523-scu
  dt-bindings: clock, reset: Add econet EN751221
parents cc8f74d3 98266d5f 67229973 858f6273 d8b03452

Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml

+5 −1
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ properties: 
      - enum:

          - airoha,en7523-scu

          - airoha,en7581-scu

          - econet,en751221-scu



  reg:

    items:
@@ -67,7 +68,9 @@ allOf: 
  - if:

      properties:

        compatible:

          const: airoha,en7581-scu

          enum:

            - airoha,en7581-scu

            - econet,en751221-scu

    then:

      properties:

        reg:
@@ -98,3 +101,4 @@ examples: 
              #reset-cells = <1>;

      };

    };

Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml

0 → 100644
+46 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/eswin,eic7700-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Eswin EIC7700 SoC clock controller



maintainers:

  - Yifeng Huang <huangyifeng@eswincomputing.com>

  - Xuyang Dong <dongxuyang@eswincomputing.com>



description:

  The clock controller generates and supplies clock to all the modules

  for eic7700 SoC.



properties:

  compatible:

    const: eswin,eic7700-clock



  reg:

    maxItems: 1



  clocks:

    items:

      - description: External 24MHz oscillator clock



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    clock-controller@51828000 {

        compatible = "eswin,eic7700-clock";

        reg = <0x51828000 0x300>;

        clocks = <&xtal24m>;

        #clock-cells = <1>;

    };

Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

+35 −5
Original line number Diff line number Diff line
@@ -28,19 +28,30 @@ properties: 
      - renesas,r9a07g044-cpg # RZ/G2{L,LC}

      - renesas,r9a07g054-cpg # RZ/V2L

      - renesas,r9a08g045-cpg # RZ/G3S

      - renesas,r9a08g046-cpg # RZ/G3L

      - renesas,r9a09g011-cpg # RZ/V2M



  reg:

    maxItems: 1



  clocks:

    maxItems: 1

    minItems: 1

    items:

      - description: Clock source to CPG can be either from external clock

                     input (EXCLK) or crystal oscillator (XIN/XOUT).

      - description: ETH0 TXC clock input

      - description: ETH0 RXC clock input

      - description: ETH1 TXC clock input

      - description: ETH1 RXC clock input



  clock-names:

    description:

      Clock source to CPG can be either from external clock input (EXCLK) or

      crystal oscillator (XIN/XOUT).

    const: extal

    minItems: 1

    items:

      - const: extal

      - const: eth0_txc_tx_clk

      - const: eth0_rxc_rx_clk

      - const: eth1_txc_tx_clk

      - const: eth1_rxc_rx_clk



  '#clock-cells':

    description: |
@@ -74,6 +85,25 @@ required: 
  - '#power-domain-cells'

  - '#reset-cells'



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: renesas,r9a08g046-cpg

    then:

      properties:

        clocks:

          minItems: 5

        clock-names:

          minItems: 5

    else:

      properties:

        clocks:

          maxItems: 1

        clock-names:

          maxItems: 1



additionalProperties: false



examples:

Documentation/devicetree/bindings/mfd/syscon.yaml

+2 −0
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ select: 
          - cirrus,ep7209-syscon2

          - cirrus,ep7209-syscon3

          - cnxt,cx92755-uc

          - econet,en751221-chip-scu

          - freecom,fsg-cs2-system-controller

          - fsl,imx93-aonmix-ns-syscfg

          - fsl,imx93-wakeupmix-syscfg
@@ -173,6 +174,7 @@ properties: 
              - cirrus,ep7209-syscon2

              - cirrus,ep7209-syscon3

              - cnxt,cx92755-uc

              - econet,en751221-chip-scu

              - freecom,fsg-cs2-system-controller

              - fsl,imx93-aonmix-ns-syscfg

              - fsl,imx93-wakeupmix-syscfg

MAINTAINERS

+10 −0
Original line number Diff line number Diff line
@@ -9096,6 +9096,8 @@ F: arch/mips/boot/dts/econet/ 
F:	arch/mips/econet/

F:	drivers/clocksource/timer-econet-en751221.c

F:	drivers/irqchip/irq-econet-en751221.c

F:	include/dt-bindings/clock/econet,en751221-scu.h

F:	include/dt-bindings/reset/econet,en751221-scu.h









ECRYPT FILE SYSTEM









M:	Tyler Hicks <code@tyhicks.com>








@@ -9495,6 +9497,14 @@ T:	git https://github.com/eswincomputing/linux-next.git







F:	Documentation/devicetree/bindings/riscv/eswin.yaml









F:	arch/riscv/boot/dts/eswin/

















ESWIN EIC7700 CLOCK DRIVER









M:	Yifeng Huang <huangyifeng@eswincomputing.com>









M:	Xuyang Dong <dongxuyang@eswincomputing.com>









S:	Maintained









F:	Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml









F:	drivers/clk/eswin/









F:	include/dt-bindings/clock/eswin,eic7700-clock.h

















ET131X NETWORK DRIVER









M:	Mark Einon <mark.einon@gmail.com>









S:	Odd Fixes