Commit 69d09a26 authored by Simona Vetter's avatar Simona Vetter
Browse files

Merge tag 'drm-intel-next-2025-07-04' of... 

Merge tag 'drm-intel-next-2025-07-04' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-next

drm/i915 feature pull #2 for v6.17:

Features and functionality:
- Add drm_panic support for both i915 and xe drivers (Jocelyn Falempe)
- Add initial flip queue implementation, disabled by default, for LNL and PTL
  (Ville)
- Add support for Wildcat Lake (WCL) display, version 30.02 (Matt Roper, Matt
  Atwood, Dnyaneshwar)
- Extend drm_panel and follower support to DDI eDP (Arun)

Refactoring and cleanups:
- Make all global state objects opaque (Jani)
- Move display works to display specific unordered workqueue (Luca)
- Add and use struct drm_device based pcode interface (Jani, Lucas)
- Use clamp() instead of max()+min() combo (Ankit)
- Simplify wait for power well disable (Jani)
- Various stylistics cleanups and renames (Jani)

Fixes:
- Deal with loss of pipe DMC state (Ville)
- Fix PTL HDCP2 stream status check (Suraj)
- Add workaround for ADL-P DKL PHY DP and HDMI (Nemesa)
- Fix skl_print_wm_changes() stack usage with KMSAN (Arnd Bergmann)
- Fix PCON capability reads on non-branch devices (Chaitanya)
- Fix which platforms have ultra joiner (Ankit)

DRM core changes:
- Add ttm_bo_kmap_try_from_panic() for xe drm_panic support (Jocelyn Falempe)
- Add private pointer to struct drm_scanout buffer for xe/i915 drm_panic support
  (Jocelyn Falempe)

Merges:
- Backmerge drm-next for drm_panel and xe changes (Jani)

Signed-off-by: default avatarSimona Vetter <simona.vetter@ffwll.ch>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/6d728bf6ef23681b00dfbc7da9aeae41042dee02@intel.com
parents 17d081ef d6a59ee8

Documentation/gpu/i915.rst

+8 −2
Original line number Diff line number Diff line
@@ -112,10 +112,10 @@ panel self refresh. 
Atomic Plane Helpers

--------------------



.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c

.. kernel-doc:: drivers/gpu/drm/i915/display/intel_plane.c

   :doc: atomic plane helpers



.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c

.. kernel-doc:: drivers/gpu/drm/i915/display/intel_plane.c

   :internal:



Asynchronous Page Flip
@@ -204,6 +204,12 @@ DMC Firmware Support 
.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c

   :internal:



DMC Flip Queue

--------------------



.. kernel-doc:: drivers/gpu/drm/i915/display/intel_flipq.c

   :doc: DMC Flip Queue



DMC wakelock support

--------------------

drivers/gpu/drm/i915/Makefile

+3 −2
Original line number Diff line number Diff line
@@ -218,12 +218,11 @@ i915-$(CONFIG_HWMON) += \ 
# modesetting core code

i915-y += \

	display/hsw_ips.o \

	display/i9xx_plane.o \

	display/i9xx_display_sr.o \

	display/i9xx_plane.o \

	display/i9xx_wm.o \

	display/intel_alpm.o \

	display/intel_atomic.o \

	display/intel_atomic_plane.o \

	display/intel_audio.o \

	display/intel_bios.o \

	display/intel_bo.o \
@@ -265,6 +264,7 @@ i915-y += \ 
	display/intel_fbc.o \

	display/intel_fdi.o \

	display/intel_fifo_underrun.o \

	display/intel_flipq.o \

	display/intel_frontbuffer.o \

	display/intel_global_state.o \

	display/intel_hdcp.o \
@@ -283,6 +283,7 @@ i915-y += \ 
	display/intel_pch.o \

	display/intel_pch_display.o \

	display/intel_pch_refclk.o \

	display/intel_plane.o \

	display/intel_plane_initial.o \

	display/intel_pmdemand.o \

	display/intel_psr.o \

drivers/gpu/drm/i915/display/hsw_ips.c

+6 −9
Original line number Diff line number Diff line
@@ -5,8 +5,9 @@ 


#include <linux/debugfs.h>



#include <drm/drm_print.h>



#include "hsw_ips.h"

#include "i915_drv.h"

#include "i915_reg.h"

#include "intel_color_regs.h"

#include "intel_de.h"
@@ -18,8 +19,6 @@ 
static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(crtc_state);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *i915 = to_i915(crtc->base.dev);

	u32 val;



	if (!crtc_state->ips_enabled)
@@ -40,7 +39,7 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state) 


	if (display->platform.broadwell) {

		drm_WARN_ON(display->drm,

			    snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL,

			    intel_pcode_write(display->drm, DISPLAY_IPS_CONTROL,

					      val | IPS_PCODE_CONTROL));

		/*

		 * Quoting Art Runyan: "its not safe to expect any particular
@@ -66,8 +65,6 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state) 
bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(crtc_state);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *i915 = to_i915(crtc->base.dev);

	bool need_vblank_wait = false;



	if (!crtc_state->ips_enabled)
@@ -75,7 +72,7 @@ bool hsw_ips_disable(const struct intel_crtc_state *crtc_state) 


	if (display->platform.broadwell) {

		drm_WARN_ON(display->drm,

			    snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, 0));

			    intel_pcode_write(display->drm, DISPLAY_IPS_CONTROL, 0));

		/*

		 * Wait for PCODE to finish disabling IPS. The BSpec specified

		 * 42ms timeout value leads to occasional timeouts so use 100ms
@@ -268,7 +265,7 @@ int hsw_ips_compute_config(struct intel_atomic_state *state, 
			return PTR_ERR(cdclk_state);



		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */

		if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)

		if (crtc_state->pixel_rate > intel_cdclk_logical(cdclk_state) * 95 / 100)

			return 0;

	}

drivers/gpu/drm/i915/display/i9xx_plane.c

+30 −6
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ 
#include "i9xx_plane.h"

#include "i9xx_plane_regs.h"

#include "intel_atomic.h"

#include "intel_atomic_plane.h"

#include "intel_bo.h"

#include "intel_de.h"

#include "intel_display_irq.h"

#include "intel_display_regs.h"
@@ -23,6 +23,7 @@ 
#include "intel_fb.h"

#include "intel_fbc.h"

#include "intel_frontbuffer.h"

#include "intel_plane.h"

#include "intel_sprite.h"



/* Primary plane formats for gen <= 3 */
@@ -336,7 +337,7 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state, 
	if (ret)

		return ret;



	ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,

	ret = intel_plane_check_clipping(plane_state, crtc_state,

					 DRM_PLANE_NO_SCALING,

					 DRM_PLANE_NO_SCALING,

					 i9xx_plane_has_windowing(plane));
@@ -905,6 +906,27 @@ static const struct drm_plane_funcs i8xx_plane_funcs = { 
	.format_mod_supported_async = intel_plane_format_mod_supported_async,

};



static void i9xx_disable_tiling(struct intel_plane *plane)

{

	struct intel_display *display = to_intel_display(plane);

	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

	u32 dspcntr;

	u32 reg;



	dspcntr = intel_de_read_fw(display, DSPCNTR(display, i9xx_plane));

	dspcntr &= ~DISP_TILED;

	intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);



	if (DISPLAY_VER(display) >= 4) {

		reg = intel_de_read_fw(display, DSPSURF(display, i9xx_plane));

		intel_de_write_fw(display, DSPSURF(display, i9xx_plane), reg);



	} else {

		reg = intel_de_read_fw(display, DSPADDR(display, i9xx_plane));

		intel_de_write_fw(display, DSPADDR(display, i9xx_plane), reg);

	}

}



struct intel_plane *

intel_primary_plane_create(struct intel_display *display, enum pipe pipe)

{
@@ -1047,6 +1069,8 @@ intel_primary_plane_create(struct intel_display *display, enum pipe pipe) 
		}

	}



	plane->disable_tiling = i9xx_disable_tiling;



	modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_TILING_X);



	if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
@@ -1151,7 +1175,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, 


	drm_WARN_ON(display->drm, pipe != crtc->pipe);



	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);

	intel_fb = intel_bo_alloc_framebuffer();

	if (!intel_fb) {

		drm_dbg_kms(display->drm, "failed to alloc fb\n");

		return;

drivers/gpu/drm/i915/display/intel_atomic.c

+1 −1
Original line number Diff line number Diff line
@@ -26,7 +26,7 @@ 
 *

 * The functions here implement the state management and hardware programming

 * dispatch required by the atomic modeset infrastructure.

 * See intel_atomic_plane.c for the plane-specific atomic functionality.

 * See intel_plane.c for the plane-specific atomic functionality.

 */



#include <drm/display/drm_dp_tunnel.h>